By: Konrad Schwarz (no.spam.delete@this.no.spam), July 23, 2015 3:38 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on July 23, 2015 7:31 am wrote:
> I don't think you are correct about it.
Ok, so I looked at the ARM ACE specification, ARM IHI 0022D, which also specifies AXI4. ACE is a coherency protocol defined by ARM. Chapter C8 is on barrier transactions.
I can't say that I have fully digested the specification, but it does look like signaling for barriers is from masters (e.g., processor cores) to downstream interconnects only (including a handshake). To me, it looks like the set of memory accesses (transactions) affected by a (full) synchronization barrier is defined implicitly as the memory accesses that happen to have been issued by processors ahead of or after the barrier. Interconnects must not reorder these accesses across the barrier.
In other words, any store queues in other processors would not be affected by a processor issuing a full synchronization barrier, contrary to my previous assertion.
The interconnect does delay completing some access transactions in certain cases.
> I don't think you are correct about it.
Ok, so I looked at the ARM ACE specification, ARM IHI 0022D, which also specifies AXI4. ACE is a coherency protocol defined by ARM. Chapter C8 is on barrier transactions.
I can't say that I have fully digested the specification, but it does look like signaling for barriers is from masters (e.g., processor cores) to downstream interconnects only (including a handshake). To me, it looks like the set of memory accesses (transactions) affected by a (full) synchronization barrier is defined implicitly as the memory accesses that happen to have been issued by processors ahead of or after the barrier. Interconnects must not reorder these accesses across the barrier.
In other words, any store queues in other processors would not be affected by a processor issuing a full synchronization barrier, contrary to my previous assertion.
The interconnect does delay completing some access transactions in certain cases.
