By: anon (anon.delete@this.anon.com), September 30, 2015 10:49 pm
Room: Moderated Discussions
Patrick Chase (patrickjchase.delete@this.gmail.com) on September 30, 2015 10:44 pm wrote:
> SHK (no.delete@this.mail.com) on September 29, 2015 6:38 am wrote:
> > * page split load penalities from 100 cycles to 5 (that's an improvement!)
>
> This appears to be a side-effect of having a second HW page-table walker - In a page-split-load
> scenario the core should now handle both walks in // instead of sequentially.
>
> The true benefits are much broader than that (relatively uncommon) case, though.
Are you sure this is not penalty for loads that hit the L1 and TLB?
Although 100 cycles does sound high. http://www.7-cpu.com/cpu/Haswell.html says Haswell takes is 28 cycles for what I assumed to be the same thing.
> SHK (no.delete@this.mail.com) on September 29, 2015 6:38 am wrote:
> > * page split load penalities from 100 cycles to 5 (that's an improvement!)
>
> This appears to be a side-effect of having a second HW page-table walker - In a page-split-load
> scenario the core should now handle both walks in // instead of sequentially.
>
> The true benefits are much broader than that (relatively uncommon) case, though.
Are you sure this is not penalty for loads that hit the L1 and TLB?
Although 100 cycles does sound high. http://www.7-cpu.com/cpu/Haswell.html says Haswell takes is 28 cycles for what I assumed to be the same thing.
