5-6 wide core, why no mention from Intel?

By: Alberto (git.delete@this.git.it), October 1, 2015 8:33 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on October 1, 2015 6:27 am wrote:
> Alberto (git.delete@this.git.it) on October 1, 2015 5:41 am wrote:
> > anon (anon.delete@this.anon.com) on October 1, 2015 3:21 am wrote:
> > > Alberto (git.delete@this.git.it) on October 1, 2015 1:13 am wrote:
> > > > Maynard Handley (name99.delete@this.name99.org) on September 30, 2015 4:30 pm wrote:
> > > > > Wouter Tinus (wouter.tinus.delete@this.gmail.com) on September 30, 2015 3:14 pm wrote:
> > > > > > It seems easy to argue that Skylake is a 5-wide or even 6-wide machine.
> > > > > >
> > > > > > - 5 wide decode
> > > > > > - 6 wide allocation/decoder queue
> > > > > > - 6 wide ROB
> > > > > > - 8 wide issue
> > > > > > - 8 wide retire (4/thread)
> > > > > >
> > > > > > Though Haswell already added extra two extra issue ports, this the first real increase in width
> > > > > > since the introduction of Merom back in 2006. Yet they didn't even bother to mention it at IDF :(
> > > > >
> > > > > I agree it's weird, but it doesn't seem to have bought them very much in performance
> > > > > (so maybe that's why they kept it quiet, to avoid unrealistic expectations?)
> > > > >
> > > > > http://www.anandtech.com/show/9483/intel-skylake-review-6700k-6600k-ddr4-ddr3-ipc-6th-generation/9
> > > > >
> > > > > Is it possible that they switched to something like two
> > > > > 3-wide execution clusters, and they're losing whatever
> > > > > they should have gained in cluster communication? But clustering seems a very un-Intel direction...
> > > > >
> > > > > Another possibility is what I suggested when Skylake first came out: that for Skylake Intel deliberately
> > > > > made choices that are sub-optimal for IPC, but allow higher frequency to be sustained for longer. So it's
> > > > > somewhat unfair, say, to compare 3GHz Broadwell with 3GHz Skylake, the real comparison out to be something
> > > > > like "amount of work done per second at equal power for the same sort of level of chip".
> > > > > Those numbers are all over the place:
> > > > > http://www.anandtech.com/show/9483/intel-skylake-review-6700k-6600k-ddr4-ddr3-ipc-6th-generation/17
> > > > > with 91W Skyake against 88W Broadwell sometimes behind (WinRAR,
> > > > > Sunspider, WebXPRT) sometimes 25% ahead(Octane).
> > > > >
> > > > > The spread in results seems to tell us that
> > > > > - there has been a substantial change in the micro-architecture BUT
> > > > > - that change seems rather "fragile", in that it may be parameterized
> > > > > to maximize a weighted basket of benchmarks,
> > > > > but the changes are no longer unequivocally a good idea
> > > > > for all (or even for 95%) of workloads; we're getting
> > > > > close to the territory of improves "60% of workloads by 3% and harms the other 40% by 2%".
> > > >
> > > > Come on :). Every new arc. has upsides and downsides, differences of +3% or -2% are pretty standard.
> > > > Even the very crap GeekB....!!! shows a solid 8% boost in IPC on Arstechnica over Haswell. I pretty
> > > > believe in the +10% claimed by Intel in a session of SPEC 2006 without libquantum obviously.
> > > > Don't try to find unexistent defects in a cpu, this is not respectful of the cpu team.
> > > >
> > > > Kudos to Intel to have archived this without rising the L2 size to 1MB or 3MB, allowing easy(!)
> > > > and efficent multicore SKUs for server with a smaller footprint and power consumption.
> > >
> > > Intel has broken these benchmarks completely by decreasing the latency of their gigantic 8MB L3 cache!
> > > Spending power on this useless cache is nothing but cheating intended to mislead the consumer.
> > >
> > > /Anti-Alberto
> >
> > Unfortunately for you the L3 latency is untouched and the L2 latency is
>
> L3 latency is effectively lower, according to the numbers shown, therefore Intel is cheating.
>
> > higher of one cycle. So the situation is even worser than in haswell.
> >
> > Nice try.....go to Techreport instead to spread fud
>
> Exactly! Now you know how it feels. Next time hopefully you'll think twice
> before taking it upon yourself to regurgitate your rubbish into ARM threads.

Rubbish is always useful in the golden plated, a little childish and uncritical ARM world, it is a sort of back to the realty thing, a realty in which have a weight the physical limits of materials and equipment.

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TopicPosted ByDate
Update to Intel Optimization ManualSHK2015/09/29 05:38 AM
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    gather speedGabriele Svelto2015/09/29 12:00 PM
  Update to Intel Optimization ManualTim McCaffrey2015/09/29 11:18 AM
    Update to Intel Optimization ManualSHK2015/09/29 12:04 PM
      Update to Intel Optimization ManualAnon2015/09/29 02:23 PM
    Update to Intel Optimization Manualnone2015/09/29 10:31 PM
      Update to Intel Optimization ManualMichael S2015/09/30 04:24 AM
    Update to Intel Optimization ManualMichael S2015/09/30 04:30 AM
      Update to Intel Optimization ManualTim McCaffrey2015/09/30 10:01 AM
  5-6 wide core, why no mention from Intel?Wouter Tinus2015/09/30 02:14 PM
    5-6 wide core, why no mention from Intel?Maynard Handley2015/09/30 03:30 PM
      5-6 wide core, why no mention from Intel?Alberto2015/10/01 12:13 AM
        5-6 wide core, why no mention from Intel?anon2015/10/01 02:21 AM
          5-6 wide core, why no mention from Intel?Alberto2015/10/01 04:41 AM
            5-6 wide core, why no mention from Intel?anon2015/10/01 05:27 AM
              5-6 wide core, why no mention from Intel?Alberto2015/10/01 08:33 AM
                5-6 wide core, why no mention from Intel?juanrga2015/10/01 10:24 AM
        5-6 wide core, why no mention from Intel?Maynard Handley2015/10/01 08:57 AM
    5-6 wide core, why no mention from Intel?juanrga2015/10/01 03:59 AM
      5-6 wide core, why no mention from Intel?Wouter Tinus2015/10/01 02:48 PM
        5-6 wide core, why no mention from Intel?juanrga2015/10/03 03:17 AM
          5-6 wide core, why no mention from Intel?Wouter Tinus2015/10/03 11:19 AM
            Are you kidding? (NT)juanrga2015/10/04 05:30 AM
              Are you kidding?Wouter Tinus2015/10/04 03:18 PM
                Are you kidding?juanrga2015/10/05 09:46 AM
                  Are you kidding?David Kanter2015/10/05 11:24 AM
                    Are you kidding?anon2015/10/05 09:26 PM
                    Are you kidding?Linus Torvalds2015/10/07 04:49 AM
                      Are you kidding?juanrga2015/10/07 10:46 AM
                        Are you kidding?anon2015/10/07 06:21 PM
                  Are you kidding?Wouter Tinus2015/10/05 01:25 PM
                    Are you kidding?juanrga2015/10/06 10:17 AM
                      Are you kidding?Stubabe2015/10/07 12:17 AM
                        Are you kidding?juanrga2015/10/07 10:56 AM
                          Amazing...Wouter Tinus2015/10/07 11:31 AM
                            Amazing...juanrga2015/10/07 03:45 PM
                          Are you kidding?Stubabe2015/10/07 11:57 AM
                            Are you kidding?juanrga2015/10/07 03:59 PM
                          Are you kidding?Wilco2015/10/07 02:07 PM
                            Are you kidding?juanrga2015/10/07 04:33 PM
      5-6 wide core, why no mention from Intel?Eric Bron2015/10/04 04:18 AM
    5-6 wide core, why no mention from Intel?David Kanter2015/10/01 09:01 AM
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        Optimal number and kind of execution unitsPatrick Chase2015/10/01 04:38 PM
          Optimal number and kind of execution unitsI.S.T.2015/10/01 05:10 PM
            Optimal number and kind of execution unitsPatrick Chase2015/10/01 11:39 PM
          Optimal number and kind of execution unitsExophase2015/10/01 10:11 PM
          Optimal number and kind of execution unitsjuanrga2015/10/02 05:14 AM
      LD/ST unitsSHK2015/10/01 11:11 AM
        LD/ST unitsDavid Kanter2015/10/01 12:54 PM
          LD/ST unitsSHK2015/10/02 04:55 AM
            LD/ST unitsJukka Larja2015/10/02 09:49 PM
        LD/ST unitsMaynard Handley2015/10/01 01:01 PM
          LD/ST unitsanon2015/10/01 09:54 PM
      5-6 wide core, why no mention from Intel?Maynard Handley2015/10/01 12:57 PM
        5-6 wide core, why no mention from Intel?David Kanter2015/10/01 03:49 PM
          5-6 wide core, why no mention from Intel?Maynard Handley2015/10/01 06:21 PM
          5-6 wide core, why no mention from Intel?Exophase2015/10/01 10:07 PM
            5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 12:10 AM
              5-6 wide core, why no mention from Intel?Megol2015/10/02 03:39 AM
                5-6 wide core, why no mention from Intel?Michael S2015/10/02 04:27 AM
                5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 09:37 AM
                  5-6 wide core, why no mention from Intel?noko2015/10/02 05:19 PM
              5-6 wide core, why no mention from Intel?Exophase2015/10/02 06:43 AM
                5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 09:45 AM
                  5-6 wide core, why no mention from Intel?Exophase2015/10/02 10:23 AM
          5-6 wide core, why no mention from Intel?Wilco2015/10/02 12:48 PM
            5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 01:25 PM
              5-6 wide core, why no mention from Intel?Wilco2015/10/02 02:26 PM
              5-6 wide core, why no mention from Intel?noko2015/10/02 05:45 PM
                5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 06:54 PM
            5-6 wide core, why no mention from Intel?David Kanter2015/10/02 01:59 PM
              5-6 wide core, why no mention from Intel?Wilco2015/10/02 02:59 PM
                5-6 wide core, why no mention from Intel?David Kanter2015/10/02 03:15 PM
                  5-6 wide core, why no mention from Intel?Wilco2015/10/02 04:06 PM
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                      LDP/STP usage in AArch64 for 403.gccWilco2015/10/03 03:02 AM
                        LDP/STP usage in AArch64 for 403.gccnone2015/10/03 03:11 AM
                          LDP/STP usage in AArch64 for 403.gccWilco2015/10/03 03:37 AM
                            LDP/STP usage in AArch64 for 403.gccnone2015/10/03 04:37 AM
                              LDP/STP usage in AArch64 for 403.gccWilco2015/10/03 05:26 AM
                  5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 04:24 PM
              5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 03:07 PM
  Update to Intel Optimization Manualanon2015/09/30 04:43 PM
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    Update to Intel Optimization Manualanon2015/09/30 10:49 PM
    Update to Intel Optimization Manualnone2015/09/30 10:50 PM
    Update to Intel Optimization ManualDavid Kanter2015/10/01 12:52 PM
      Update to Intel Optimization ManualPatrick Chase2015/10/01 04:16 PM
        Update to Intel Optimization Manualanon2015/10/01 10:45 PM
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