By: SHK (no.delete@this.mail.com), October 2, 2015 4:55 am
Room: Moderated Discussions
David Kanter (dkanter.delete@this.realworldtech.com) on October
[...]
> ISTR reading that hte POWER8 (or maybe it was the latest z?) used around 2W in the L1D.
>
> IBM's L1D is super aggressive, but it's also a write-through design, which
> simplifies many flows (at the cost of worse overall performance).
>
> David
My guess would be system-z, i think that since z12EC they have the L2D directory inside L1D and they check both every load, so an L1D-miss/L2D-hit has IIRC just 6-cycles latecy on z13.
But it's clearly a power hungry scheme.
OTOH i wish Intel had more high TDP-oriented chips, now that watercooling is becoming more mainstream it would be nice to have a >200W TDP not just for overclocking (which just makes the whole memory wall worse) but to have a more aggressive microarch.
Just my 0.2$, it's probabily a way to small niche for Intel to invest into.
[...]
> ISTR reading that hte POWER8 (or maybe it was the latest z?) used around 2W in the L1D.
>
> IBM's L1D is super aggressive, but it's also a write-through design, which
> simplifies many flows (at the cost of worse overall performance).
>
> David
My guess would be system-z, i think that since z12EC they have the L2D directory inside L1D and they check both every load, so an L1D-miss/L2D-hit has IIRC just 6-cycles latecy on z13.
But it's clearly a power hungry scheme.
OTOH i wish Intel had more high TDP-oriented chips, now that watercooling is becoming more mainstream it would be nice to have a >200W TDP not just for overclocking (which just makes the whole memory wall worse) but to have a more aggressive microarch.
Just my 0.2$, it's probabily a way to small niche for Intel to invest into.
