Wouter Tinus (wouter.tinus.delete@this.gmail.com) on October 7, 2015 12:31 pm wrote:
> First you basically claim that 1=2 because 1x2=2, now I guess you realized that and accuse
> us of nitpicking on terminology. Which would be fine, if you were not the one who started
> this whole subthread by proposing your very own definition of wideness. Of course we're
> going to nitpick about terminology, as terminology is the topic at hand.
>
> You have been meaning to talk about issue width all along, as I suspected and suggested
> in my first response to you. There, Skylake and Haswell are indeed equals.
>
> So man up and admit that your definition didn't make sense, or at least stop
> accusing others of pushing you into the hole you that dug for yourself.

No. The first time I replied your question about width, I wrote: "First were would agree on how to measure the wide of a core."

Different conventions will give different sizes. Haswell can be 4-wide, 5-wide, or 8-wide depending on how you measure wide. For me (and for others) Haswell is 8-wide because can retire up to 8 uops per cycle. I quote Carey Patterson again:

So what does that make the width of Haswell/Broadwell? It's really an 8-issue processor at heart, since up to 8 un-fused μops can be fetched, issued and completed per cycle if they're paired/fused in just the right way (and an un-fused μop is the most direct equivalent of a simple RISC instruction), but even experts disagree on exactly what to call the width of such a design, since 4-issue would also be valid, in terms of fused μops, which is what the processor mostly "thinks in terms of" for tracking purposes, and 5-issue is also valid if thinking in terms of original x86 instructions.

If you don't like it you can use another convention to measure width and claim Haswell is 4-wide.

P.S.: Since you claim now that definitions used by others don't make sense. I will just say your pretension to use decoder to define width doesn't make sense, because it doesn't account for over-provisioned designs.