Are you kidding?

By: juanrga (nospam.delete@this.juanrga.com), October 7, 2015 3:59 pm
Room: Moderated Discussions
Stubabe (Stubabe.delete@this.nospam.com) on October 7, 2015 12:57 pm wrote:
> juanrga (nospam.delete@this.juanrga.com) on October 7, 2015 11:56 am wrote:
> > Stubabe (Stubabe.delete@this.nospam.com) on October 7, 2015 1:17 am wrote:
> >
> > > So if YOU are claiming Haswell is a 8-wide design by counting fused uops as 2 (and I think you are the
> > > only one here that is) then Skylake is 12wide allocate with 16 wide retire. However, these values are
> > > clearly unrealistic not least because Haswell cannot sustain 8-issue under any possible non-microcoded
> > > x86 code sequence. So a more reasonable description is Haswell is 4 wide and Skylake is 6 wide.
> > >
> >
> > Since this thread is spinning towards another useless terminology/convention
> > fight. I will just add this relevant quote and move on:
> >
> >
A processor such as Core i*4/i*5 Haswell/Broadwell, for example, can decode up to 5 x86 instructions
> > per cycle, producing a maximum of up to 4 fused μops per cycle, which are then stored in an L0 μop
> > cache, from which up to 4 fused μops per cycle are fetched, then register-renamed and placed into a
> > reorder buffer, from which up to 8 un-fused individual μops are issued per cycle to the functional units,
> > where they proceed down the various pipelines until they complete, whereupon up to 4 fused μops per
> > cycle can be committed and retired. So what does that make the width of Haswell/Broadwell? It's really
> > an 8-issue processor at heart, since up to 8 un-fused μops can be fetched, issued and completed per
> > cycle if they're paired/fused in just the right way (and an un-fused μop is the most direct equivalent
> > of a simple RISC instruction), but even experts disagree on exactly what to call the width of such a
> > design, since 4-issue would also be valid, in terms of fused μops, which is what the processor mostly
> > "thinks in terms of" for tracking purposes, and 5-issue is also valid if thinking in terms of original
> > x86 instructions.
Of course, this width-labelling conundrum is largely academic, since no processor
> > is likely to actually sustain such high levels of ILP when running real-world code anyway.

> >
>
> This isn't an issue of different terminology but your inconsistent terminology.

I wrote "terminology/convention fight" because many threads here finish with useless discussion about terminology and/or conventions. A recent example was some people saying other "you call server is not a server, only what I call server is a real server".

I noted at the start of the thread that the width of a core depends of the convention used. If you use one convention then Haswell is 4-wide, if you use another convention then it is 8-wide.

There is no inconsistency, just different ways to define things.

> If you want to use the definition YOU used to describe Haswell as 8-wide then by YOUR standard Skylake
> can retire 16 uops, which is unrealistic and that's why I suggested its a silly terminology to use.

I don't know how many instructions Skylake can issue, execute, and retire. And I said that I avoid to consider Skylake until I read some detailed discussion of the architecture. But I can say you something for sure. I will not say it is 5-wide or 6-wide, because I will not use decoder neither fused-uops to measure its wide.

> There is no possible code sequence that can produce the right mixture of fused uops to sustain 8 issue
> in Haswell since that would require 4 load units as there are no fused exec-store ops and two units
> are dedicated to the store path (Store Address and Store Data).

Apart from ignoring that the definition refers to the maximum allowed by the muarch, not to sustained rate, and apart from ignoring the last phrase in the above quote "Of course, this width-labelling conundrum is largely academic, since no processor is likely to actually sustain such high levels of ILP when running real-world code anyway" which is your point?
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TopicPosted ByDate
Update to Intel Optimization ManualSHK2015/09/29 05:38 AM
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    Update to Intel Optimization ManualSHK2015/09/29 12:04 PM
      Update to Intel Optimization ManualAnon2015/09/29 02:23 PM
    Update to Intel Optimization Manualnone2015/09/29 10:31 PM
      Update to Intel Optimization ManualMichael S2015/09/30 04:24 AM
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        5-6 wide core, why no mention from Intel?anon2015/10/01 02:21 AM
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            5-6 wide core, why no mention from Intel?anon2015/10/01 05:27 AM
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                5-6 wide core, why no mention from Intel?juanrga2015/10/01 10:24 AM
        5-6 wide core, why no mention from Intel?Maynard Handley2015/10/01 08:57 AM
    5-6 wide core, why no mention from Intel?juanrga2015/10/01 03:59 AM
      5-6 wide core, why no mention from Intel?Wouter Tinus2015/10/01 02:48 PM
        5-6 wide core, why no mention from Intel?juanrga2015/10/03 03:17 AM
          5-6 wide core, why no mention from Intel?Wouter Tinus2015/10/03 11:19 AM
            Are you kidding? (NT)juanrga2015/10/04 05:30 AM
              Are you kidding?Wouter Tinus2015/10/04 03:18 PM
                Are you kidding?juanrga2015/10/05 09:46 AM
                  Are you kidding?David Kanter2015/10/05 11:24 AM
                    Are you kidding?anon2015/10/05 09:26 PM
                    Are you kidding?Linus Torvalds2015/10/07 04:49 AM
                      Are you kidding?juanrga2015/10/07 10:46 AM
                        Are you kidding?anon2015/10/07 06:21 PM
                  Are you kidding?Wouter Tinus2015/10/05 01:25 PM
                    Are you kidding?juanrga2015/10/06 10:17 AM
                      Are you kidding?Stubabe2015/10/07 12:17 AM
                        Are you kidding?juanrga2015/10/07 10:56 AM
                          Amazing...Wouter Tinus2015/10/07 11:31 AM
                            Amazing...juanrga2015/10/07 03:45 PM
                          Are you kidding?Stubabe2015/10/07 11:57 AM
                            Are you kidding?juanrga2015/10/07 03:59 PM
                          Are you kidding?Wilco2015/10/07 02:07 PM
                            Are you kidding?juanrga2015/10/07 04:33 PM
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    5-6 wide core, why no mention from Intel?David Kanter2015/10/01 09:01 AM
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        5-6 wide core, why no mention from Intel?David Kanter2015/10/01 03:49 PM
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                            LDP/STP usage in AArch64 for 403.gccnone2015/10/03 04:37 AM
                              LDP/STP usage in AArch64 for 403.gccWilco2015/10/03 05:26 AM
                  5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 04:24 PM
              5-6 wide core, why no mention from Intel?Maynard Handley2015/10/02 03:07 PM
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    Update to Intel Optimization Manualanon2015/09/30 10:49 PM
    Update to Intel Optimization Manualnone2015/09/30 10:50 PM
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      Update to Intel Optimization ManualPatrick Chase2015/10/01 04:16 PM
        Update to Intel Optimization Manualanon2015/10/01 10:45 PM
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