lurker (lurker9000.delete@this.realemail.mail) on October 29, 2015 3:12 pm wrote:
> Regarding Zen performance, a guy who worked for AMD (at least his linkedin profile says that) and
> who, as he claims, worked on designing L2 cache for Zen and K12 said that their focus was to be
> competitive against Intel. He no longer works there but apparently his old colleague who still
> works there said Zen chips have already been tested and so far "it has met all expectation" and
> they "haven't found any significant bottlenecks". Apparently they haven't finalized the specifications
> for the clocks and TDP, but their partners in server market are "very excited".
> It's not much detail, but I think if there was a problem from having
> only 2 AGUs, it would count as a significant bottleneck.
> Also this is my first post ever, I just usually lurk here and this is the first
> time I have something useful to add to the discussion. Please no bully.

First of all - welcome to RWT, glad to hear your perspective.

My guess is that everything you say is true...and that AMD isn't intending to hit the HPC market. They have 128b vectors (since that's all ARM supports), which simply isn't wide enough to be competitive with Skylake. So giving up on a third AGU makes sense. The third AGU is probably most helpful for HPC (where they cannot compete anyway) and isn't a particularly small unit in terms of design complexity and impact on the load/store buffer.

David