By: lurker (lurker9000.delete@this.realemail.mail), October 30, 2015 2:41 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on October 30, 2015 3:14 am wrote:
> I'm doubtful that lacking a 3rd AGU will make much difference in SMT-friendly loads. Those are usually
> either constrained by memory or branch misses leaving plenty of opportunities for the other thread
> to use the AGUs. The only scenario where this might be limiting if there's more than two threads
> but even there this doesn't seem to be a major problem: if you look at POWER8 the only realistic
> scenario in which it can make full use both its dual load and dual load-store pipes are carefully
> tuned vector kernels; and that's a processor which supports up to 8 threads per core!
Thanks for clearing that up. Guess 2 AGUs shouldn't be a big problem then.
> I'm doubtful that lacking a 3rd AGU will make much difference in SMT-friendly loads. Those are usually
> either constrained by memory or branch misses leaving plenty of opportunities for the other thread
> to use the AGUs. The only scenario where this might be limiting if there's more than two threads
> but even there this doesn't seem to be a major problem: if you look at POWER8 the only realistic
> scenario in which it can make full use both its dual load and dual load-store pipes are carefully
> tuned vector kernels; and that's a processor which supports up to 8 threads per core!
Thanks for clearing that up. Guess 2 AGUs shouldn't be a big problem then.