anon (anon.delete@this.anon.com) on October 30, 2015 6:54 am wrote:
> I don't think it's that much. It has 2 "LU" and 2 "LSU" units, so I think there is a maximum combination of
> 4 per cycle. However the mix I'm not entirely sure of, and there is conflicting information I have not yet
> dug through enough. Some say 2 loads + 2 loads-or-stores per cycle. Some 4 loads or 1 store per cycle. Some
> says a store uses a slot in both LSU and LU, which would be 4 loads, 2 loads + 1 store, or 2 stores.

The POWER8 user manual (available here behind an IBM login or here directly) discuss this in great detail, there's multiple combinations that are possible and the exact limitations aren't spelled out too clearly. On the surface:

- The two LU units can do both GPR loads and FP/VSX/VMX loads
- The two LSU units can do both GPR loads and all type of stores

But, GPR stores employ both an LSU and an LU for their two components (store_agen, store_data), FP/VSX/VMX stores employ both an LSU and an LSU. This limits the potential combinations to:

- 4 GPR loads
- 2 GPR loads and 2 FP/VSX/VMX loads
- 2 GPR stores
- 2 GPR loads and 2 FP/VSX/VMX stores

That being said the description of the L1 cache mentions that it can support up to 4 loads and 1 store per cycle when there are no bank conflicts and that each bank can support either 2 loads or 1 store. The store port in the L1 cache is used either for L2 cache reloads or writes and is 16 bytes wide. The store port is independent from the store instructions (those write in the SDQ, not the L1 directly) so my guess is that the L1 cache can absorb two 8-byte stores per cycle as long as they are adjacent, and thus can be drained together from the SDQ. This also means that while the 2 GPR loads & 2 FP/VSX/VMS stores scenario is possible it cannot be sustained when using vectors as it would generate 32 bytes worth of stores per cycle.