Poindexter (cherullo.delete@this.gmail.com) on October 31, 2015 2:47 pm wrote:
> I find it funny that you like to tout pipe numbers, but you never discuss
> other architectural features that have direct impact in this discussion:
> - MOV elimination
> - Store-to-load forwarding
> - Memory reordering and memory disambiguation
> - Instruction fusing

I think the point is that we don't really know the details on the rest of the architecture? So I think it's not a problem if he focuses on the details we do know.

> - Never provided any connection between Haswell's increased IPC over Ivy Bridge to the third AGU.

I have no idea if this is the reason for it, but in Haswell SMT works a lot better than in Ivy. Say if you were doing multi-core compilation in Ivy, the whole system would just freeze up until the work is completed. It seems to be a bit better in Haswell so perhaps that extra AGU helps?

> Regarding the FPU, you never mention that Zen's FPU doesn't share ports with the integer ALUs like
> Haswell does. You never mention that Zen's FPU has more ports and units than Haswell's. You only seem
> to care about maximum throughput (in the e-penis sense), which frankly, is not that interesting.

Is it really that much of an advantage that FPU doesn't share ports with interger ALUs? In SMT perhaps?
I guess the separate ports for the ADD and MUL units are an advantage in some workloads.
And to be fair maximum throughput is important in HPC, right? I don't think it's that important in general workloads though.