By: juanrga (nospam.delete@this.juanrga.com), November 1, 2015 7:41 am
Room: Moderated Discussions
Heikki Kultala (hkultala.delete@this.iki.fi) on October 31, 2015 2:19 pm wrote:
> juanrga (nospam.delete@this.juanrga.com) on October 31, 2015 6:20 am wrote:
> > Heikki Kultala (hkultala.delete@this.iki.fi) on October 30, 2015 3:45 pm wrote:
> >
> > > > The real reason why AMD Zen is stuck with 128bit units can be cache/memory bottlenecks or Skybridge
> > > > (pin and inside compatibility of both K12 and Zen) or simply saving die space or .
> > >
> > > The width of the FPU's has nothing to do with the external pins of the
> > > processor. There are zillion different-width buses between them.
> > >
> > >
> >
> > Textbook-example of straw-man fallacy.
> >
> > You took my sketchy description of the Skybridge project,
> > then cherry-picked the "pin" part, ignored the "and inside" part, and wrote giving the impression
> > of refuting my argument, while actually refuting an argument which was not advanced by me.
>
> no, just a point to counter _one part_ of your argument, not your whole argument.
No part of my argument was about what you pretend. One part of my argument was about cache/memory bottlenecks, another part was about Skybride compatibility with K12 and another was about saving die space. In no part I said that 128bit is related to pins...
Your post was a textbook-example of straw-man fallacy.
> > I will try again to explain my argument.
> >
> > Skybridge was AMD project for pin and inside compatibility between ARM and x86 products. Pin
> > compatibility would produce a socket compatible for both the ARM and the x86 SoCs from AMD.
> >
> > Inside compatibility would produce a set of ARM and x86 cores easily interchangeable
> > inside the SoC for simplifying AMD business (specially the semicustom division).
> > You can get the concept on this diagram applied to 'small' cores
> >
> >
> >
> > Same about 'big' cores, indeed Zen was presented as the "sister core" of K12.
> >
> > AMD couldn't release a K12 core with 128bit SIMD units and a Zen core with 256bit SIMD units
> > within the Skybridge project, because that hypothetical Zen would require wider datapaths,
> > wider memory units, higher cache throughput,... ruining the lego-like replacement.
>
> They would only need wider datapath between L1 cache and LSUs when widening the FPU.
> And L1 is part of the core.
>
> Datapath between L1 and L2 caches is completely different thing. They
> need not to be same width than datapaths between L1 and LSUs.
Note how I wrote "cache" and you discuss caches...
> So it's very easy to have the different cores having same L1DL2
> width but different LSUL1D width and different datapath width.
>
> The one thing that should match with the different cache levels is the cache block size(to make coherence
> easier etc.) And that has been same 64 bytes for most processor cores for the last >15 years.
>
> > But Skybridge was finally canceled. Thus maybe the reason for Zen
> > having 128bit units is some of those other reasons mentioned above.
>
> Skybridge was cancelled much later than at the point when the FPU width
> of Zen was chosen, You do not change that kind of things late.
>
I wrote "maybe" because I don't know when Skybridge was canceled. I only know when the announcement was made.
> juanrga (nospam.delete@this.juanrga.com) on October 31, 2015 6:20 am wrote:
> > Heikki Kultala (hkultala.delete@this.iki.fi) on October 30, 2015 3:45 pm wrote:
> >
> > > > The real reason why AMD Zen is stuck with 128bit units can be cache/memory bottlenecks or Skybridge
> > > > (pin and inside compatibility of both K12 and Zen) or simply saving die space or .
> > >
> > > The width of the FPU's has nothing to do with the external pins of the
> > > processor. There are zillion different-width buses between them.
> > >
> > >
> >
> > Textbook-example of straw-man fallacy.
> >
> > You took my sketchy description of the Skybridge project,
> > then cherry-picked the "pin" part, ignored the "and inside" part, and wrote giving the impression
> > of refuting my argument, while actually refuting an argument which was not advanced by me.
>
> no, just a point to counter _one part_ of your argument, not your whole argument.
No part of my argument was about what you pretend. One part of my argument was about cache/memory bottlenecks, another part was about Skybride compatibility with K12 and another was about saving die space. In no part I said that 128bit is related to pins...
Your post was a textbook-example of straw-man fallacy.
> > I will try again to explain my argument.
> >
> > Skybridge was AMD project for pin and inside compatibility between ARM and x86 products. Pin
> > compatibility would produce a socket compatible for both the ARM and the x86 SoCs from AMD.
> >
> > Inside compatibility would produce a set of ARM and x86 cores easily interchangeable
> > inside the SoC for simplifying AMD business (specially the semicustom division).
> > You can get the concept on this diagram applied to 'small' cores
> >
> >
> >
> > Same about 'big' cores, indeed Zen was presented as the "sister core" of K12.
> >
> > AMD couldn't release a K12 core with 128bit SIMD units and a Zen core with 256bit SIMD units
> > within the Skybridge project, because that hypothetical Zen would require wider datapaths,
> > wider memory units, higher cache throughput,... ruining the lego-like replacement.
>
> They would only need wider datapath between L1 cache and LSUs when widening the FPU.
> And L1 is part of the core.
>
> Datapath between L1 and L2 caches is completely different thing. They
> need not to be same width than datapaths between L1 and LSUs.
Note how I wrote "cache" and you discuss caches...
> So it's very easy to have the different cores having same L1DL2
> width but different LSUL1D width and different datapath width.
>
> The one thing that should match with the different cache levels is the cache block size(to make coherence
> easier etc.) And that has been same 64 bytes for most processor cores for the last >15 years.
>
> > But Skybridge was finally canceled. Thus maybe the reason for Zen
> > having 128bit units is some of those other reasons mentioned above.
>
> Skybridge was cancelled much later than at the point when the FPU width
> of Zen was chosen, You do not change that kind of things late.
>
I wrote "maybe" because I don't know when Skybridge was canceled. I only know when the announcement was made.
