By: Peter McGuinness (peter.mcguinness.delete@this.gobrach.com), August 2, 2016 7:11 am
Room: Moderated Discussions
David,
Unfortunately, your assumptions about TBR are in error. This test actually demonstrates conclusively that these GPUs are NOT tile based; the previous commenter who asserted that the apparent tile organisation is due to optimised cache-to-memory transfer patterns is much closer to the truth.
The fundamental characteristic of a tile based renderer, deferred or not, is that each tile is rendered to completion in on-chip memory and only after all visible objects have been rendered is the final result written out to display memory. This means that except in some very rare circumstances you will never see a partially rendered tile so the fact that occluded triangles are visible in the video is conclusive evidence that nvidia is still using a classic brute force immediate mode approach.
Peter
Unfortunately, your assumptions about TBR are in error. This test actually demonstrates conclusively that these GPUs are NOT tile based; the previous commenter who asserted that the apparent tile organisation is due to optimised cache-to-memory transfer patterns is much closer to the truth.
The fundamental characteristic of a tile based renderer, deferred or not, is that each tile is rendered to completion in on-chip memory and only after all visible objects have been rendered is the final result written out to display memory. This means that except in some very rare circumstances you will never see a partially rendered tile so the fact that occluded triangles are visible in the video is conclusive evidence that nvidia is still using a classic brute force immediate mode approach.
Peter
