Peter McGuinness (peter.mcguinness.delete@this.gobrach.com) on August 2, 2016 8:11 am wrote:
> David,
> Unfortunately, your assumptions about TBR are in error. This test actually demonstrates conclusively
> that these GPUs are NOT tile based; the previous commenter who asserted that the apparent tile organisation
> is due to optimised cache-to-memory transfer patterns is much closer to the truth.
>
> The fundamental characteristic of a tile based renderer, deferred or not, is that each tile is rendered
> to completion in on-chip memory and only after all visible objects have been rendered is the final result
> written out to display memory. This means that except in some very rare circumstances you will never
> see a partially rendered tile so the fact that occluded triangles are visible in the video is conclusive
> evidence that nvidia is still using a classic brute force immediate mode approach.

Peter, if you read my article you will see I never claimed Nvidia was doing tiled *rendering*, they are doing tiled rasterizing. Of course their approach is totally different than IMG.

But I suspect this captures most of the benefits of TBDR.

David