By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), May 10, 2017 7:15 pm
Room: Moderated Discussions
steve m (steve.marton.delete@this.gmail.com) on May 10, 2017 5:16 pm wrote:
> The GPU presumably dispatches in an order that maximizes cache coherence, coherence
> with render target tiling, and maybe coherence in the various internal buffers (not
> "tile" buffers). Generally some sort of spacial coherence is implied by all that.
It's been confirmed by nVidia that this is only used to exploit locality in the L2 cache, there's no tiling going on. See the slides from their GDC presentation.
> The GPU presumably dispatches in an order that maximizes cache coherence, coherence
> with render target tiling, and maybe coherence in the various internal buffers (not
> "tile" buffers). Generally some sort of spacial coherence is implied by all that.
It's been confirmed by nVidia that this is only used to exploit locality in the L2 cache, there's no tiling going on. See the slides from their GDC presentation.