By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), May 17, 2017 5:43 am
Room: Moderated Discussions
steve m (steve.marton.delete@this.gmail.com) on May 16, 2017 11:49 am wrote:
> Well, I have to eat my words partially. It seems that both Nvidia (https://www.techpowerup.com/231129/on-nvidias-tile-based-rendering)
> and AMD (https://videocardz.com/65406/exclusive-amd-vega-presentation) have made the ROPs
> a client of the L2, and they are attempting to render triangles in screen space tiles. This
> minimizes L2 thrashing, similar to the other considerations that enforce spacial locality
> that I mentioned in my previous post.
I hadn't seen that Vega presentation yet, thanks for the pointer.
> Note that both Nvidia and AMD emphasize being immediate mode renderers, which implies that draw calls are
> executed serially, not deferred! So most of the advantages of TBDR don't apply, neither the drawbacks.
No, a TBDR requires a radically different architecture and to my knowledge only ImgTec was able to pull it off successfully. Even the Adreno's which do have an on-chip tile don't do deferred rendering.
> However, the behavior in David's video is puzzling in that context, if Nvidia is trying
> to rasterize in tile order. Why would the GPU go ahead and rasterize triangles in future
> tiles before it's done with one tile? Seems like unnecessary cache thrashing to me.
Possibly load-balancing to prevent keeping the rasterizers from being idle while the pixels in the previous tile are being shaded. If the L2 can hold two tiles at the same time then it should be fine.
> Well, I have to eat my words partially. It seems that both Nvidia (https://www.techpowerup.com/231129/on-nvidias-tile-based-rendering)
> and AMD (https://videocardz.com/65406/exclusive-amd-vega-presentation) have made the ROPs
> a client of the L2, and they are attempting to render triangles in screen space tiles. This
> minimizes L2 thrashing, similar to the other considerations that enforce spacial locality
> that I mentioned in my previous post.
I hadn't seen that Vega presentation yet, thanks for the pointer.
> Note that both Nvidia and AMD emphasize being immediate mode renderers, which implies that draw calls are
> executed serially, not deferred! So most of the advantages of TBDR don't apply, neither the drawbacks.
No, a TBDR requires a radically different architecture and to my knowledge only ImgTec was able to pull it off successfully. Even the Adreno's which do have an on-chip tile don't do deferred rendering.
> However, the behavior in David's video is puzzling in that context, if Nvidia is trying
> to rasterize in tile order. Why would the GPU go ahead and rasterize triangles in future
> tiles before it's done with one tile? Seems like unnecessary cache thrashing to me.
Possibly load-balancing to prevent keeping the rasterizers from being idle while the pixels in the previous tile are being shaded. If the L2 can hold two tiles at the same time then it should be fine.
