Early decode of unconditional jumps

By: Peter Cordes (peter.delete@this.cordes.ca), August 9, 2016 11:35 am
Room: Moderated Discussions
This question is the result of discussion in comments on my answer on this Stack Overflow question.

Travis (travis.downs.delete@this.gmail.com) on August 9, 2016 10:44 am wrote:
> A question that was raised, however, is about fixed length archs - can these architectures avoid use of BTB
> entries for fixed-target branches by decoding such jumps early and redirecting fetch? That is, avoiding the
> use of the BTB for branches whose targets are fixed in the instruction, leaving the BTB resources for branches
> which may actually vary (e.g., indirect jumps). Do any of the common fixed-length archs actually do this?

I was guessing that early scan of the instruction stream for direct jumps might be used as a supplementary mechanism for the BTB, to shorten the bubbles when the usual mechanism is cold. But it probably wouldn't be worth the power budget, since the "regular" case for a fixed-insn-length ISA is probably not nearly as bad as x86 (see that Stack Overflow link for Broadwell experimental numbers).

If you can avoid bubbles for the common case of unconditional jumps where the branch target isn't also a jump, this could help a lot in reducing the need for a large BTB. (A jump that targets another jump is also going to be a problem for a BTB, though, right?)

Anyway, I'd be curious to hear what the tradeoffs are like for something like AArch64 (low power targeting potentially bloated GUI code) vs. PPC (high power targeting HPC workloads).

> [1] In some cases I supposed unconditional jumps may disappear when a post-decode cache
> instruction is used that simply stores the trace with unconditional jumps elided. I'm pretty
> sure Netburst does this, but I don't remember if modern Intel uop cache does it?

IDK about P4, but jmp on SnB-family definitely still executes as a uop, so it has to come from somewhere (i.e. isn't elided). I think the uop cache has some trace-like aspects, but it caches in small lines, and has to split at 32B x86 code boundaries. (So eliding would present a problem when a jmp is a jump *target*.)
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TopicPosted ByDate
Branch/jump target predictionTravis2016/08/09 09:44 AM
  Early decode of unconditional jumpsPeter Cordes2016/08/09 11:35 AM
    Early decode of unconditional jumpsExophase2016/08/09 12:29 PM
  pipelines are too long, noHeikki Kultala2016/08/09 11:37 AM
    pipelines are too long, nono name2016/08/09 06:17 PM
      pipelines are too long, noWilco2016/08/10 01:43 AM
        pipelines are too long, noPaul A. Clayton2016/08/10 07:44 PM
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                            Branch/jump target prediction -8David Kanter2016/08/19 11:23 PM
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                            Branch/jump target prediction -8Simon Farnsworth2016/08/19 08:28 AM
                              Branch/jump target prediction -8Simon Farnsworth2016/08/19 08:40 AM
                            Branch/jump target prediction -8David Kanter2016/08/22 11:05 PM
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                        Branch/jump target prediction -8anon2016/08/26 07:14 AM
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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
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                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
                        The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 09:36 AM
                          The (wrong) state of trace caches on modern CPUsExophase2016/08/25 10:32 AM
                        The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 10:12 AM
                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
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        Branch/jump target predictionGabriele Svelto2016/08/11 12:15 PM
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