By: Heikki Kultala (firstname.lastname@example.org), August 9, 2016 11:37 am
Room: Moderated Discussions
> A question that was raised, however, is about fixed length archs - can these architectures avoid use of BTB
> entries for fixed-target branches by decoding such jumps early and redirecting fetch? That is, avoiding the
> use of the BTB for branches whose targets are fixed in the instruction, leaving the BTB resources for branches
> which may actually vary (e.g., indirect jumps). Do any of the common fixed-length archs actually do this?
Modern pipelines are way too long for this, the branch cannot be decoded early enough when just the i-cache access takes multipl clock cycles.
And even the only 5-stage pipeline of most of the "original" RISC processors needed the one delay slot for this.