pipelines are too long, no

By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), August 10, 2016 1:43 am
Room: Moderated Discussions
no name (no.delete@this.name.com) on August 9, 2016 7:17 pm wrote:
> Heikki Kultala (hkultala.delete@this.iki.fi) on August 9, 2016 12:37 pm wrote:
> > Modern pipelines are way too long for this, the branch cannot be decoded
> > early enough when just the i-cache access takes multipl clock cycles.
>
> ++
>
> Any amount of pipelining means you need a BTB. You need to generate the address for the next cycle
> while the branch is read out of the cache on the current cycle. The fact so few people get that a
> block address (not the exact branch address) is typically used for predictions is infuriating.

Even the main BTB is pipelined and too slow on modern cores, which is why you need a separate micro-BTB.

> Even the RISC-V manual said something this in their ISA manual "another advantage of a fused compare-and-branch
> instruction is that branches are observed earlier in the front-end instruction stream, and so can be
> predicted earlier."

That's quite incorrect (and why would you mention such implementation details in an ISA manual???). It is an advantage of delayed branches. Compare&branch actually makes branch prediction harder as basic blocks are now smaller and contain fewer non-branch instructions.

> Sure, by not making it 2 instructions it's marginally ahead in the instruction
> stream, but 90% of the time it will be within the same fetch block and make no difference to the predictor.
> The BTB will be consulted regardless of the presence of a branch within the block.

Indeed. But the BTB does have to work harder as there are more branches per fetch.

Wilco
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TopicPosted ByDate
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    pipelines are too long, nono name2016/08/09 06:17 PM
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