Branch/jump target prediction

By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), August 10, 2016 4:14 pm
Room: Moderated Discussions
Megol (golem960.delete@this.gmail.com) on August 10, 2016 3:25 pm wrote:
>
> Can't argue against that, however the problems were mostly elsewhere.

I agree that a lot of P4 weaknesses were exacerbated by other issues, and that the legacy decoders were too weak. But the legacy decoders were too weak partly because people had thought that trace caches were a good idea. They aren't.

> > And it has almost nothing in common with the crap that was the P4 trace cache.
>
> So why mention it?

.. because the predecode cache is the correct way to do this, and makes the trace cache pointless.

So the BSD is very much relevant to the discussion - as a "look, here's something that actually works better, and that Intel does that largely replaces the broken trace cache".

> What kind of workloads do you run where instruction cache coherency is problematic?

Umm. Like almost all of them?

Do you realize how bad the P4 was at coherency? To the point that compiler-generated code that didn't actually do self-modifying things at all had huge problems, just because the coherence "solution" that Intel picked sucked.

Yeah, it's less of an issue on architectures that don't actually need coherency in the first place, but that wasn't what was discussed. What was claimed was that the P4 trace cache was "awesome".

It really really wasn't.

> Really...

Really. Trust me. Compilers had to be changed because of it.

Yes, you can argue that that was due to another bad implementation issue, but the oddity comes almost directly from the fact that coherence gets more complicated, so then you do odd/bad things to simplify the problems.

So the coherency issues were pretty much caused by the trace cache. The fact is, trace caches need more care and complexity in this area.

> Most branches _are_ very predictable, for those that aren't -> don't create a trace.
>Fixed.

Bullshit.

You don't know which branches are predictable to begin with. Also, even the "very predictable" ones tend to be about 99%, which isn't actually that predictable after all - it causes problems when you end up having code overlap anyway.

And btw, those benchmarks that show how predictable branches are? Yeah, they aren't really all that indicative of real code that people actually run.

It all boils down to the fact that you basically need to have the non-trace-cache case execute pretty much as quickly as the trace case, and the whole trace cache ends up being a lot of complexity for very little advantage. You can't actually try to skimp on the "legacy" decoders after all.

So you're much better off doing just a L0 I$ predecoded cache on an instruction boundary level, and forget entirely about the traces.

> Perhaps you should look up what a trace cache is before stating things like that?

Yeah, let's just imagine that I worked for a company that did very similar things and actually generated traces on real loads.

In other words, I haven't just masturbated over academic papers like you apparently do. I do know how they work.

They suck.

Linus

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