Branch/jump target prediction -8

By: Ricardo B (ricardo.b.delete@this.xxxxx.xx), August 16, 2016 9:33 am
Room: Moderated Discussions
⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on August 16, 2016 9:23 am wrote:
> Ricardo B (ricardo.b.delete@this.xxxxx.xx) on August 16, 2016 7:39 am wrote:
> > ⚛ (0xe2.0x9a.0x9b.delete@this.gmail.com) on August 16, 2016 6:40 am wrote:
> > >
> > > The outcome of a conditional branch depends on data (not on
> > > code). An instruction prefix can help branch prediction
> > > only if the prefix is mentioning a register or a memory location containing the prediction(s).
> >
> > You're suggesting to have a register/memory access in the path of the branch prediction logic?
> > That will just stall the fetch/decode pipeline.
> > That's like operating without branch prediction and just stalling
> > the pipeline until the branch instruction is retired.
>
> What would be an alternative option to improving branch prediction over Skylake's other
> than computing the prediction and somehow feeding it to the parts of CPU which need it?
>
> If a CPU needs to know the value of the register used by the conditional branch 8 cycles before the
> branch opcode enters the pipeline, then the compiler/programmer will emit branch-with-prediction-in-register
> only in case the register can be filled with information 8 cycles before the branch.
>
> An alternative option that comes to my mind is: Conditional jump after 8 instructions. That is, the conditional
> branch instruction enters the pipeline, the CPU postpones its execution, starts counting from 1 to 8, and after
> it executes/retires the 8th instruction it executes the postponed conditional branch instruction.
>
> Question: How many conditional branches in real-world code are predictable
> 8 cycles before the branch instruction enters the CPU pipeline?

Some early RISCs had a branch delay slot: the next instruction after a branch was always taken.
However, that brings us to the first problem: it's micro-architecture dependent.
It worked for the initial implementations (5-state single issue pipelines) but was nothing but a nuisance for future ones.

The other problem is the following. If I understood you correctly, you were proposing something like
mov reg, hint # Store hint into reg
... lots of instructions later ...
jmp reg, label # Jump with hint

The problem is that in a big OoO core like Skylake, the front end has no idea about the state of the execution of the "mov reg, hint" instruction.
For all we know, "reg" may not have been assigned a physical register yet, or it's physical register hasn't been written (thus has some garbage value).

And the sort of logic that is needed to sort this state out is big and complex: that's why CPUs have so many pipeline stages, to split this sort of complex logic.

Deeply pipelined CPUs is a need which arises from the need to split complex logic over multiple clock stages.
Branch prediction is a need which arises from pipelines, but branch prediction logic needs to be kept simple so it can work in a single (or few) clock stages.
If a branch prediction algorithm cannot be implemented in fast logic, it's worthless. We'd be better of by stalling the pipeline until the branch instruction is actually resolved.
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TopicPosted ByDate
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