Branch/jump target prediction

By: Megol (golem960.delete@this.gmail.com), August 19, 2016 6:42 am
Room: Moderated Discussions
Linus Torvalds (torvalds.delete@this.linux-foundation.org) on August 10, 2016 5:14 pm wrote:
> Megol (golem960.delete@this.gmail.com) on August 10, 2016 3:25 pm wrote:
> >
> > Can't argue against that, however the problems were mostly elsewhere.
>
> I agree that a lot of P4 weaknesses were exacerbated by other issues, and that
> the legacy decoders were too weak. But the legacy decoders were too weak partly
> because people had thought that trace caches were a good idea. They aren't.
>
> > > And it has almost nothing in common with the crap that was the P4 trace cache.
> >
> > So why mention it?
>
> .. because the predecode cache is the correct way to do this, and makes the trace cache pointless.

No it doesn't as it doesn't solve the same problem.

> So the BSD is very much relevant to the discussion - as a "look, here's something that actually
> works better, and that Intel does that largely replaces the broken trace cache".
>
> > What kind of workloads do you run where instruction cache coherency is problematic?
>
> Umm. Like almost all of them?
>
> Do you realize how bad the P4 was at coherency? To the point that compiler-generated
> code that didn't actually do self-modifying things at all had huge problems,
> just because the coherence "solution" that Intel picked sucked.

Okay I misunderstood. While data instruction cache coherency is indeed a problem in the P4 it is most commonly referred to as a problem for self-modifying code. What is commonly called coherency is keeping caches on different processors/cores updated.

> Yeah, it's less of an issue on architectures that don't actually need coherency in the first place,
> but that wasn't what was discussed. What was claimed was that the P4 trace cache was "awesome".
>
> It really really wasn't.
>
> > Really...
>
> Really. Trust me. Compilers had to be changed because of it.

Strange that one have to change compilers to run better on newer processors, never happened before I say.

> Yes, you can argue that that was due to another bad implementation issue, but the oddity comes almost directly
> from the fact that coherence gets more complicated, so then you do odd/bad things to simplify the problems.
>
> So the coherency issues were pretty much caused by the trace cache. The
> fact is, trace caches need more care and complexity in this area.

Yes.

> > Most branches _are_ very predictable, for those that aren't -> don't create a trace.
> >Fixed.
>
> Bullshit.
>
> You don't know which branches are predictable to begin with. Also, even the "very
> predictable" ones tend to be about 99%, which isn't actually that predictable
> after all - it causes problems when you end up having code overlap anyway.

Not knowing which branches are predictable isn't a problem - delay trace creation until one does is trivial in a good frontend design. The P4 couldn't do that given it's extremely narrow legacy decoder. But I have never been talking about using the P4 as a model.

> And btw, those benchmarks that show how predictable branches are? Yeah, they
> aren't really all that indicative of real code that people actually run.

Like GCC? Do you realize it is trivial to use performance counters to see how many branch mispredicts real world code have? Most branches are predicted well for real world code.

> It all boils down to the fact that you basically need to have the non-trace-cache case execute pretty
> much as quickly as the trace case, and the whole trace cache ends up being a lot of complexity for
> very little advantage. You can't actually try to skimp on the "legacy" decoders after all.

Congratulations! Perhaps you will someday understand that saying trace caches aren't a bad concept isn't the same thing as saying the P4 had a good front-end. It hadn't and it isn't really relevant to this thread that doesn't start out as Pentium 4 worship!

> So you're much better off doing just a L0 I$ predecoded cache on an
> instruction boundary level, and forget entirely about the traces.

That solves a mostly different problem than the trace cache.

> > Perhaps you should look up what a trace cache is before stating things like that?
>
> Yeah, let's just imagine that I worked for a company that did very
> similar things and actually generated traces on real loads.

Similar things sure. But doing trace scheduling isn't the same thing as doing trace caches.

Trace caches were created to increase fetch bandwidth for wide superscalar processors for realistic real-world code where branches are common. It is an alternative to things like multi-way branch predictors, collapsing instruction buffers etc.

> In other words, I haven't just masturbated over academic
> papers like you apparently do. I do know how they work.

It is obvious that you don't know how they work - you don't even understand why they were created in the first place!

If reading academic papers, verifying that they measure the correct things and building ones understanding on that is masturbation (I interpret that as "fucking around without real results" as any other would be puerile) I wonder what we should call the act of not understanding a topic, incorrectly thinking one have experience in the area and then in an act of ego-stroking loudly call the world to see this "expertise"?

Doing a Linus Torvalds perhaps?

> They suck.

--

I thought I had replied to this a long time ago, can't see it so either it was a failed posting or aggressive enough to warrant moderation [unlikely].
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                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
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