Branch/jump target prediction

By: David Kanter (, August 19, 2016 11:34 pm
Room: Moderated Discussions
Maynard Handley ( on August 19, 2016 11:46 am wrote:
> Megol ( on August 19, 2016 7:42 am wrote:
> > Linus Torvalds ( on August 10, 2016 5:14 pm
> > Congratulations! Perhaps you will someday understand that saying trace caches aren't a
> > bad concept isn't the same thing as saying the P4 had a good front-end. It hadn't and
> > it isn't really relevant to this thread that doesn't start out as Pentium 4 worship!
> >
> > > So you're much better off doing just a L0 I$ predecoded cache on an
> > > instruction boundary level, and forget entirely about the traces.
> >
> > That solves a mostly different problem than the trace cache.
> >
> > > > Perhaps you should look up what a trace cache is before stating things like that?
> > >
> > > Yeah, let's just imagine that I worked for a company that did very
> > > similar things and actually generated traces on real loads.
> >
> > Similar things sure. But doing trace scheduling isn't the same thing as doing trace caches.
> >
> > Trace caches were created to increase fetch bandwidth for wide superscalar processors
> > for realistic real-world code where branches are common. It is an alternative to things
> > like multi-way branch predictors, collapsing instruction buffers etc.
> >
> > > In other words, I haven't just masturbated over academic
> > > papers like you apparently do. I do know how they work.
> >
> > It is obvious that you don't know how they work - you don't
> > even understand why they were created in the first place!
> >
> > If reading academic papers, verifying that they measure the correct things and building ones understanding
> > on that is masturbation (I interpret that as "fucking around
> > without real results" as any other would be puerile)
> > I wonder what we should call the act of not understanding a topic, incorrectly thinking one have experience
> > in the area and then in an act of ego-stroking loudly call the world to see this "expertise"?
> >
> I suspect the real resolution here is that there may have been a narrow
> window of time during which trace caches make sense, but no longer.
> Look at the description I gave of modern fetch. That's basically an on-going dynamic
> construction of traces. So why would statically constructed traces be better?
> - the predictor used for the dynamic construction of traces will obviously be better than that
> for static construction since it is constantly being updated (and even if the static trace
> construction feels it can use multi-cycle predictors for really high quality prediction, as
> I mentioned above, the same multi-cycle predictors can be used on a modern processor)
> - obviously the trace cache takes up transistors and there are hassle issues in
> terms of making sure it stays in sync with all the other processor/memory state
> - there might theoretically be a power advantage to using traces, but even that, I suspect
> is minimal. Most of your time is generally spent in loops, and a loop buffer can act
> like a very minimal trace cache --- which does however handle the hot case
> So I suspect traces made sense during a period when people wanted to pull in lots of instructions
> but weren't able to devote enough transistors to doing so properly (with a truly aggressive fetch
> front-end). But those days are over --- we have plenty of resources to apply to fetch and static traces
> are basically a poor cousin to what we're doing today. Maybe they'd be a good choice for an intermediate
> low-end chip (ARM M4 sort of thing) in terms of the performance vs power tradeoff?
> But for a high-end chip I don't see it.

I don't think instruction delivery is close to solved at all. Trace caches are problematic, but fetch and decode is a huge problem.

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TopicPosted ByDate
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                        Branch/jump target prediction -8Maynard Handley2016/08/18 06:27 PM
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                            Branch/jump target prediction -8David Kanter2016/08/19 11:23 PM
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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
                      That's not trueDavid Kanter2016/08/23 08:39 AM
                        That's not trueMaynard Handley2016/08/23 08:56 AM
                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
                        The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 09:36 AM
                          The (wrong) state of trace caches on modern CPUsExophase2016/08/25 10:32 AM
                        The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 10:12 AM
                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
                            The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 11:20 AM
                              The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 12:34 PM
        Branch/jump target predictionGabriele Svelto2016/08/11 12:15 PM
  Branch/jump target predictionGabriele Svelto2016/08/20 06:21 AM
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