Branch/jump target prediction

By: Megol (golem960.delete@this.gmail.com), August 21, 2016 9:27 am
Room: Moderated Discussions
sylt (no.delete@this.thanks.com) on August 19, 2016 11:48 am wrote:
> Megol (golem960.delete@this.gmail.com) on August 19, 2016 7:42 am wrote:
> > Okay I misunderstood. While data instruction cache coherency is indeed a problem in
> > the P4 it is most commonly referred to as a problem for self-modifying code. What is
> > commonly called coherency is keeping caches on different processors/cores updated.
> >
>
> Although I don't know much about the P4 trace cache specifically I think the main point here was that the
> processor never knows *IF* there is a need for coherency (i.e. self modifying code) or not. Coherency always
> comes into play regardless of if it is needed by the application or not. If the coherency is complicated
> and thus maybe a bit pessimistically implemented you could have lots of false evictions for code that is
> not really self modifying but maybe merely wrote some "near miss" data or similar pitfalls.

It is problematic - but again mostly because the P4 was a bad design (my personal opinion - some parts of it was beautiful but most were at the level of "what the f**k were they thinking").
--
Let's compare to a IMHO better design with a trace cache: Have a reasonably sized, snooping L1 I cache followed by 3-4 legacy format decoders followed by trace creation logic (which can be a mix of hardware and software) and then a reasonably sized L0 I cache of the trace type followed by internal format decoders and then issue logic etc.
Code that doesn't hit in the trace cache will go through the L1 cache and then the legacy decoders. A branch mispredict that doesn't hit the trace cache will skip the trace creation logic and the trace cache/internal decoders which reduces restart latency.
Self-modifying code etc. will require flushing of traces (theoretically one could do a trace repair but that is probably to complex for real machines) _but_ while the trace cache is flushed the execution unit can use the traditional fetch mechanism with similar delays that current x86 machines have - unless of course the traditional front end have been powered down.

Sounds like a decoded µop cache? It is similar but not the same thing. The decoded µop cache is much easier to add to an existing design and is more conservative as proper trace creation isn't needed. It can shave some complexities in decoding x86 instruction too.
But it also doesn't get the core advantages of a trace cache as a way to "solve" the instruction fetch problem.
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TopicPosted ByDate
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                    Branch/jump target prediction -8anon2016/08/16 09:09 AM
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                      Branch/jump target prediction -82016/08/18 05:21 PM
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                            Branch/jump target prediction -8David Kanter2016/08/19 11:23 PM
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                        Branch/jump target prediction -8anon2016/08/26 07:14 AM
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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
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                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
                        The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 09:36 AM
                          The (wrong) state of trace caches on modern CPUsExophase2016/08/25 10:32 AM
                        The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 10:12 AM
                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
                            The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 11:20 AM
                              The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 12:34 PM
        Branch/jump target predictionGabriele Svelto2016/08/11 12:15 PM
  Branch/jump target predictionGabriele Svelto2016/08/20 06:21 AM
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