The (apparent) state of trace caches on modern CPUs

By: anon (anon.delete@this.anon.com), August 22, 2016 11:36 pm
Room: Moderated Discussions
Exophase (exophase.delete@this.gmail.com) on August 22, 2016 8:55 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on August 22, 2016 3:10 pm wrote:
> > That sounds a HELL OF A LOT like a trace cache that dare not say its name...
>
> It's not though. A trace cache and a post-decode cache perform two completely different functions.
> The former addresses fetch bandwidth/power/area and the latter decode bandwidth/power/area. Netburst's
> was only called a trace cache but it was actually both. Sandy Bridge does not cache traces.
>
> Note that Sandy Bridge onward still retain a (post-decode) loop buffer as well.
>
> > (However P4 had trace cache as 8-way, 12K µops, SB has direct mapped 1.5K µops)
>
> The uop cache in SB and its successors is 8-way.
>
> > The Intel slide for this
> > http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/2
> > is conveniently vague, talking as it does about an ability to "stitch" across branches in the control flow.
> >
>
> Read the RWT article instead: http://www.realworldtech.com/sandy-bridge/4/
>
> > As always it would be interesting to know what Apple does. Both companies obviously want
> > to save power and improve performance. A decoded µop cache of traces seems to be more
> > helpful towards this goal than a pure decoded µop loop buffer, allowing as it does more
> > code of a more varied nature than just a single straight line loop trace.
> >
>
> There's much less incentive to use a post-decode cache on ARM than x86, especially if it's more
> optimized for AArch64 (no idea if this is true yet to any extent whatsoever for Apple)

ARM since about Cortex A9 has used a post decode loop buffer, and I think they still do on their 64 bit uarchs. Even on that ISA, icache, fetch, decode use a large proportion of total core power.
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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
                      That's not trueDavid Kanter2016/08/23 08:39 AM
                        That's not trueMaynard Handley2016/08/23 08:56 AM
                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
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                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
                            The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 11:20 AM
                              The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 12:34 PM
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