The (wrong) state of trace caches on modern CPUs

By: Michael S (already5chosen.delete@this.yahoo.com), August 25, 2016 2:28 am
Room: Moderated Discussions
Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com) on August 25, 2016 2:38 am wrote:
> > "
> > With the Intel Sandybridge [45] processor, Intel introduced
> > a μop cache instead of a loop buffer. μop caches
> > tradeoff some of the power efficiency of loop caches in exchange
> > for capturing more instructions and behaviors.
> > Thus codes which frequent and simple loops may be better
> > served by a traditional loop cache, however μop caches
> > are more robust and able to derive benefit more irregular
> > codes. Essentially, μop caches operate as traditional
> > caches which hold decoded instructions. However, they share
> > some characteristics with loop caches. [b]In current
> > commercial implementations, μop caches encode predicted branch
> > paths.[/b] If branch paths differ from previously
> > predicted paths, like loop caches the μop cache must be flushed and refilled.
> > "
>
> well, the above excerpt contains roughly one error per
> line, it looks like this PhD was not properly reviewed
>

His linkedin profile rather impressive for a young man.
Including:
Engineering Intern
Intel Corporation
May 2010 – December 2010 (8 months)

• Worked on the Haswell performance modeling team.
• Performed early stage feature evaluation for a future generation processor..
• Extensive C++ coding on an out of order processor simulator.


As a non-native English speaker I see a grammar of above quote as problematic, but may be for natives it's o.k? Or, may be, there are typing mistakes, like "Thus codes which frequent" must be "Thus codes with frequent" or "derive benefit more irregular" should be "derive benefit for more irregular"

But yes, SB has *both* Decoded ICache and ability to utilize Micro-op Queue as small loop cache.
And yes, SB Decoded ICache stores uOps in program order rather than in predicted branch path order.
And yes, when "branch paths differ from previously predicted paths" Decoded ICache is *not* flushed.


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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
                      That's not trueDavid Kanter2016/08/23 08:39 AM
                        That's not trueMaynard Handley2016/08/23 08:56 AM
                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
                        The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 09:36 AM
                          The (wrong) state of trace caches on modern CPUsExophase2016/08/25 10:32 AM
                        The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 10:12 AM
                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
                            The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 11:20 AM
                              The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 12:34 PM
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