The (wrong) state of trace caches on modern CPUs

By: Maynard Handley (name99.delete@this.name99.org), August 25, 2016 12:34 pm
Room: Moderated Discussions
Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com) on August 25, 2016 12:20 pm wrote:
> > Hayenga's thesis [...] describes a SUBSTANTIALLY different
> > model of a decoded µop cache from what David describes.
>
> in case you missed it, he describes this based on David's
> article, see [45] in the bibliography of his thesis
>
> I'll add that, based on years of hand-on perf tuning with vTune on SNB and followers, it's clear that
> the 80+% hit rate is for real, including for code with high branch miss rate (but good code locality)

I know he refers to David's article. But what he describes is actually very different from David's article.
My guess is that he obviously knew what was being discussed inside Intel, and wanted to throw in a reference, any reference, to an existing CPU utilizing a decoded ops cache, so he used the first thing he could find as reference even though it doesn't actually match his larger point. As I said, he probably knew the discussion within Intel, and lost track of how the exact details of SB differ from the (much more sophisticated) model he had in mind for his thesis.
It's the sort of thing that happens all the time when you're at the last stage of a thesis and need to throw in a few references to prove points that you think are so obvious that they don't really need a reference, so you don't bother looking at the detail once you've found something that looks good enough.

The thesis is interesting and worth looking at. It comes across as kinda insane (in terms of the ambition and complexity) but we've seen that plenty of things that seemed insanely ambitious when proposed ten or fifteen years ago do gradually move into the real world once engineers have had enough time to mull over the idea and game out all its likely consequences and difficulties. And of course he's now at ARM, so everything I said about the relative value of a decoded ops cache for Intel vs ARM (simplify decoding vs power savings) ...
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                The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/22 02:10 PM
                  The (apparent) state of trace caches on modern CPUsExophase2016/08/22 07:55 PM
                    The (apparent) state of trace caches on modern CPUsanon2016/08/22 11:36 PM
                      The (apparent) state of trace caches on modern CPUsExophase2016/08/23 04:08 AM
                        The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:51 PM
                          The (apparent) state of trace caches on modern CPUsExophase2016/08/23 10:12 PM
                          The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/24 06:38 AM
                            The (apparent) state of trace caches on modern CPUsanon2016/08/24 07:26 PM
                    The (apparent) state of trace caches on modern CPUsMaynard Handley2016/08/23 06:48 AM
                      That's not trueDavid Kanter2016/08/23 08:39 AM
                        That's not trueMaynard Handley2016/08/23 08:56 AM
                      The (apparent) state of trace caches on modern CPUsanon2016/08/23 08:54 PM
                  The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 01:38 AM
                    The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 02:28 AM
                      The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 06:12 AM
                      The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 08:50 AM
                        The (wrong) state of trace caches on modern CPUsMichael S2016/08/25 09:36 AM
                          The (wrong) state of trace caches on modern CPUsExophase2016/08/25 10:32 AM
                        The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 10:12 AM
                          The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 11:01 AM
                            The (wrong) state of trace caches on modern CPUsEric Bron2016/08/25 11:20 AM
                              The (wrong) state of trace caches on modern CPUsMaynard Handley2016/08/25 12:34 PM
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