David Hess (davidwhess.delete@this.gmail.com) on October 22, 2016 1:26 pm wrote:
> But it only does this at half of the clock rate. Skylake has a 4 cycle load latency which pipelining
> and out of order execution neatly hide. The A10 probably has the same 4 cycle load latency that
> the A9 has but at twice the clock rate, that would become an unsustainable 8 cycles meaning that
> the core would be spending half of its time waiting lowering its IPC by a factor of 2.

I'm confused by your claim that the 4 cycle latency on Intel is hidden by "which pipelining and out of order execution", but that a latency of 8 cycles would halve the IPC?

There is nothing magic about a load-to-use latency of 4. Whether a bit of code is limited by this latency depends entirely on the code. Sometimes this latency is hidden, and often it is not (many types of pointer chasing or table lookup codes end up being limited by the L1 cache latency in practice). If the latency was 3, it could be hidden (or partially hidden) a bit more often and improve performance slightly. If it was 5, it would be hidden (or partially hidden) a bit less and performance would suffer a bit. If load-to-use latency jumped to 8, it would impact performance - but only on the most pathological cases would it halve performance (codes that are entirely L1 latency bound).