David Hess (davidwhess.delete@this.gmail.com) on October 25, 2016 9:59 pm wrote:
> Maynard Handley (name99.delete@this.name99.org) on October 24, 2016 4:27 pm wrote:
> >
> > Beyond this, the naive model suggested by David Hess assumes the A10 is clocked at maximum frequency for
> > this design. This is highly unlikely. We'll see a higher frequency limit when the A10X ships. You all
> > know the frequency I've suggested that could be clocked
> > at, based simply on the A9X vs A9 frequency scaling,
> > and what TSMC has said about their 10nm process, but scaling that to beyond 4GHz it seems reasonable to
> > say that Apple's current design would engender something more like 5 rather than 8 clocks.
>
> Our discussion is necessarily vague because we lack implementation details.
>
> I am assuming that the A10 makes maximum use of its longer cycle time either to use
> as many logic levels as possible between stages or to use the slowest logic available
> between each stage to save power. Doing otherwise would degrade performance by either
> lowering the amount of work done per cycle or increasing the power per cycle.
>
> The alternative is that Apple designed a 4 GHz processor but only operates it at 2 GHz do to power constraints.
> They could do that but a dedicated 2 GHz design would be higher performance or lower power or both.
>

Of course, it's obvious that they have designed it for the target speeds. Neither of your conclusions regarding L1 latency follow from that, however.