> Apple doesn’t always have the best performance per square millimeter,
Seems pretty clear to me that that is perf/area.

> writes Gwennap, but it makes up for it in efficiency per clock cycle,
Gwennap thinks Apple may have performed some design tricks,
> such as “large branch tables” to optimize “branch prediction”
> when carrying out instructions.
Larger branch tables count as design tricks now?

The next two paragraphs seems weird too.
Especially this:
> The A10 can deliver “nearly identical performance” to
> Intel’s “Skylake” generation of “Core” processors.
> The difference, of course, is that Intel PC chips don’t
> operate within the battery constraints of the A10.
So either he actually read that report as "The A10 is better than Skylake because it gets almost the same performance at far less power" or it's intellectual dishonesty, which would be a perfect reason to use that picture with Broadwell including the caches.


We all know that Intel sucks at designing for mobile, but I wouldn't compare the A10 with Skylake because of the vastly different design targets. I wouldn't compare Silvermont and POWER8 either. Given the power consumption Silvermont or Goldmont would've been more reasonable to compare the A10 against. It runs circles around those.

I'm just really uncomfortable with the way that article pushes the Apple agenda, considering that some people bet a lot of money on this and similar articles being correct.


Simon Farnsworth and Heikki Kultala have already explained what I meant with designing a slow core.

I won't participate in an x86 vs ARM or Intel vs Apple discussion because the first has been debated to hell and back
http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf
and the other is just pointless.