underclocked is different than designed for low clock speed

By: Maynard Handley (name99.delete@this.name99.org), October 26, 2016 10:07 am
Room: Moderated Discussions
Heikki Kultala (heikki.kultala.delete@this.tut.fi) on October 25, 2016 11:47 pm wrote:
> juanrga (noemail.delete@this.juanrga.com) on October 25, 2016 9:57 am wrote:
> > anon (spam.delete.delete@this.this.spam.com) on October 23, 2016 7:25 am wrote:
> > > juanrga (noemail.delete@this.juanrga.com) on October 23, 2016 6:09 am wrote:
> > > > anon (spam.delete@this.spam.com) on October 22, 2016 8:52 am wrote:
> > > >
> > > > > I mean
> > > >
> > > > > > Apple doesn’t always have the best performance per square millimeter,
> > > > > > writes Gwennap, but it makes up for it in efficiency per clock cycle
> > > >
> > > > > that's not how it works.
> > > >
> > > > His first claim is correct, Apple Hurricane doesn't have the best performance per area,
> > > > but this is expected because it is a latency-optimized core not a throughput optimized-core.
> > > > About his second claim if by "efficiency per clock cycle" he means IPC/Area then his claim
> > > > is wrong or right depending if he is comparing to Intel or to other ARM cores.
> > >
> > > My point is that perf = clockrate * ipc. Whether the ipc is high with low clockrates
> > > or abysmal with insane clockrates doesn't matter at all for perf/area. Same
> > > perf and same area mean same perf/area, regardless of the ipc.
> >
> > But he talks about "efficiency per clock cycle" which suggest he is talking about
> > IPC/Area, not about Perf/Area. And the superior IPC/Area of Apple chips compared
> > to Intel chips is related to ARM64 efficiency: the well-known "x86 tax".
>
> No, it's mostly is because:
>
> 1) Intel chips use longer pipelines to achieve higher clock speeds
> and the longer pipelines costs transistors and chip area.
>
> 2) Intel has much beefier SIMD side which does nothing on integer benchmarks. Run FP SIMD codes and intel has
> much better performance/clock. Intel also does have a very beefy division unit which is used quite rarely.

Beefier SIMD, yes. MUCH beefier, is more ambiguous...
- Apple apparently has three 128b pipelines, Intel has two 256b pipelines. So 512 vs 384

- A single Intel instruction can do 2x as much work --- but that instruction is longer, and Apple can decode/dispatch more of them per cycle.

- Intel has gather. ARM doesn't have that (yet...) but has 2, 3, 4-wide "rearrangers" that catch many common cases (though not generic sparse linear algebra) and which are starting to be used by LLVM, though this has taken quite some time. And ARM has the write side of this which mainstream AVX does not.


You can see this when you compare somewhat like CPUs.
Compare A10 to i5-5200U @ 2.70 GHz, which is the closest reasonable matchup I can find.
The overall single threaded scores are 3510 vs 3519 and the two scores of interest (very obviously vector friendly) are
- SGEMM 48 vs 63 GFlops
- SFFT 7 vs 9.3 GFlops

Some of the other benchmarks are likely also vectorizable (HDR? Gaussian Blur? Speech Recognition?) but we can be less certain of those.
Perhaps Intel handles doubles better (both these Geekbench tests are single), but I've no reason to believe that. (And does AVX handle 16-bit floats?)

What's certainly the case for now is that Intel has a Fortran compiling story which is, I assume, of very little interest to Apple, but which allows some SPEC codes to be compiled; and Intel has a compiler that's *probably* better than Apple's at extracting vectorization from "generic" scientific code (and certainly at doing so for a very specific set of scientific code...) but those are both irrelevant to the area/underlying hardware claim.
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