Pushing the hidden agenda

By: juanrga (noemail.delete@this.juanrga.com), October 28, 2016 2:11 am
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on October 26, 2016 3:10 am wrote:
> > Apple doesn’t always have the best performance per square millimeter,
> Seems pretty clear to me that that is perf/area.
>
> > writes Gwennap, but it makes up for it in efficiency per clock cycle,
> Gwennap thinks Apple may have performed some design tricks,
> > such as “large branch tables” to optimize “branch prediction”
> > when carrying out instructions.
> Larger branch tables count as design tricks now?
>
> The next two paragraphs seems weird too.
> Especially this:
> > The A10 can deliver “nearly identical performance” to
> > Intel’s “Skylake” generation of “Core” processors.
> > The difference, of course, is that Intel PC chips don’t
> > operate within the battery constraints of the A10.
> So either he actually read that report as "The A10 is better than Skylake because it gets
> almost the same performance at far less power" or it's intellectual dishonesty, which
> would be a perfect reason to use that picture with Broadwell including the caches.
>
>
> We all know that Intel sucks at designing for mobile, but I wouldn't compare the A10
> with Skylake because of the vastly different design targets. I wouldn't compare Silvermont
> and POWER8 either. Given the power consumption Silvermont or Goldmont would've been
> more reasonable to compare the A10 against. It runs circles around those.
>
> I'm just really uncomfortable with the way that article pushes the Apple agenda, considering
> that some people bet a lot of money on this and similar articles being correct.


Therefore if Anandtech compares Cyclone to Haswell or if compares Twister to Broadwell and Skylake, that is fine, but if MPR compares Hurricane to Skylake, that is pushing "the Apple agenda".

I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple's LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell's ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 - 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense.

[...]

Unfortunately I don't have enough data on Swift to really produce a decent comparison image. With six decoders and nine ports to execution units, Cyclone is big. As I mentioned before, it's bigger than anything else that goes in a phone. Apple didn't build a Krait/Silvermont competitor, it built something much closer to Intel's big cores. At the launch of the iPhone 5s, Apple referred to the A7 as being "desktop class" - it turns out that wasn't an exaggeration.


http://www.anandtech.com/show/7910/apples-cyclone-microarchitecture-detailed

However by the same metric there’s no question that Apple is closing the gap; A9X can compete with both Broadwell and Skylake Core M processors, and that’s something Apple couldn’t claim even a generation ago.


http://www.anandtech.com/show/9766/the-apple-ipad-pro-review/4

Thanks anon for the double standard.

>
> I won't participate in an x86 vs ARM or Intel vs Apple discussion
> because the first has been debated to hell and back
> http://research.cs.wisc.edu/vertical/papers/2013/hpca13-isa-power-struggles.pdf
> and the other is just pointless.

You cannot anonymously accuse Gwennap of pushing an agenda and then mentioning this wrong article that doesn't prove what the authors pretend. This article was discussed extensively here in an older thread. Search the details; I will offer a concise resume: the authors did everything what was possible and then a little more to increase the power consumption on the ARM part whereas reducing its performance to favor artificially the x86 chips.

I recall I did laugh the first time I did read their work. Then I concluded it couldn't be plain incompetence because each decision taken always favored the same chips. I then did search the authors and found that the main author was leading a research group whose main coworker was a Senior Research Scientist at Intel, the group is sponsored by Intel grants and some alumni got their first work at Intel.
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            Broadwell includes LLC, just for comparisionanon2016/10/22 07:52 AM
              Broadwell includes LLC, just for comparisionjuanrga2016/10/23 05:09 AM
                Broadwell includes LLC, just for comparisionanon2016/10/23 06:25 AM
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                                Broadwell includes LLC, just for comparisionSimon Farnsworth2016/10/31 03:42 AM
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                                  Broadwell includes LLC, just for comparisionMaynard Handley2016/11/01 12:37 PM
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                                      Broadwell includes LLC, just for comparisionMaynard Handley2016/11/01 06:30 PM
                                        Broadwell includes LLC, just for comparisionanon2016/11/02 05:15 AM
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                                            Broadwell includes LLC, just for comparisionanon2016/11/02 10:50 AM
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                      underclocked is different than designed for low clock speedMaynard Handley2016/10/26 09:07 AM
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                    Broadwell includes LLC, just for comparisionanon2016/10/26 02:10 AM
                      Pushing the hidden agendajuanrga2016/10/28 02:11 AM
                        Pushing the hidden agendaanon2016/10/28 03:35 AM
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