juanrga (noemail.delete@this.juanrga.com) on October 28, 2016 2:02 am wrote:
> Essentially the same rule applies upwards and downwards, only parameters vary.
>
> If your design is optimized for 4GHz and underclocking to 2GHz increases the IPC by less than 5%, then
> if your design is optimized for 2GHz, overclocking it to 4GHz will reduce the IPC by a similar amount.
> It is not like if Apple will increase the clocks and will lost half of the IPC magically.
>
> The A10 is running at 2.34GHz and the A10X will probably run near 3GHz. Apple will surely
> optimized the design for some intermediate frequency. Let us say 2.5GHz. My point is
> that Apple can target 4GHz for some future chip, miss some few IPC percents compared
> to current designs and then recover those percents via hardware improvements.
>
> We already had this kind of discussion in this forum. Initially the multiple fanboys and trolls
> in this forum claimed that Apple never never could get IPC levels similar to Intel. Then Apple
> released cyclone (which Anandtech named "Haswell-class") and the common mantra was that Apple
> had obtained that IPC level because clocks were so low as 1.4GHz. The same ignorant fanboys
> and trolls claimed that Apple couldn't increase clocks and maintain the IPC. Well Apple has
> nearly duplicated frequencies and not only maintained the IPC but increased it a bit.

The only problem with that is while you can underclock any any design, you can't overclock every design much.
Cyclone as it is won't reach 4GHz on 16nm.
I'd also guess that the A10X will have a higher TDP and can therefore afford higher Voltage to get lower tau. So d stays the same but d(abs) will be lower.