8 wide vs 6 wide

By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), October 30, 2016 1:12 pm
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on October 30, 2016 12:20 pm wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on October 30, 2016 5:00 am wrote:
> > There is nothing 8 wide in x86 cores - you can't count micro-op or macro-op
> > fusion as making a CPU wider. In fact Apple's cores are significantly wider
> > than Intel's both in the front-end and back-end. It's 4 vs 6 and 7 vs ~10.
>
>
> Why not? The fact that Intel's instruction set is CISC means that some instructions encode more than one
> RISC instruction. So if 4 x86 instructions can decode to 8 RISC instructions, and can be executed them all
> at once, I'd argue that it is technically an 8 wide front end - just one with a lot of issue restrictions
> because you have to have the 'right' 8 instructions for it to work. No different than the fact that Apple's
> front end can't handle every possible combination of 6 instructions, but are limited in some ways.

If you include micro-op fusion on x86, you also have to do the same for the ARM ISA. So loads with writeback and shift&add instructions count as 2 RISC instructions, conditionally executed shift+orr as 4 (since on x86 CSEL needs 2 micro ops). That makes Apple's cores at least 20 wide, possibly a lot more if we start to look at some of the complex load/store or NEON instructions. This is getting silly don't you think?

Similarly macro-op fusion doesn't imply a doubling of the width, otherwise Cortex-A72 would be known as 6 wide, and Apple's A10 as 12 wide...

Wilco
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