Doug S (foo.delete@this.bar.bar) on October 30, 2016 12:20 pm wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on October 30, 2016 5:00 am wrote:
> > There is nothing 8 wide in x86 cores - you can't count micro-op or macro-op
> > fusion as making a CPU wider. In fact Apple's cores are significantly wider
> > than Intel's both in the front-end and back-end. It's 4 vs 6 and 7 vs ~10.
>
>
> Why not? The fact that Intel's instruction set is CISC means that some instructions encode more than one
> RISC instruction. So if 4 x86 instructions can decode to 8 RISC instructions, and can be executed them all
> at once, I'd argue that it is technically an 8 wide front end - just one with a lot of issue restrictions
> because you have to have the 'right' 8 instructions for it to work. No different than the fact that Apple's
> front end can't handle every possible combination of 6 instructions, but are limited in some ways.
>
> If you had a CPU that could execute 11 instructions at once, so long as they were register
> moves, but a maximum of 3 if anything other than a register move was included, would
> you consider it 3 wide or 11 wide? Every wide modern core has various restrictions in
> place, so every number for front/back end width has to come with an asterisk.

Indeed and if the core stalls would it be considered 0-wide? Evidently, there is two ways to define the wide, either as a kind of average, which is not very useful because it depends on the elements of the ensemble taken to compute the average or we define wide as the maximum allowed by the architecture. Thus even if Broadwell cannot sustain 8 uops per cycle, we define it as 8-wide.

It is also useful to mention context; we were trying to explain the reasons why Broadwell core is much bigger than Hurricane core. Even if Broadwell cannot sustain 8 uops, it has all the circuitry and transistors needed to issue "up to" 8 uops, and that adds to the size of the core compared to a 6-wide Hurricane.