David Hess (davidwhess.delete@this.gmail.com) on October 25, 2016 10:37 pm wrote:
> Travis (travis.downs.delete@this.gmail.com) on October 25, 2016 10:22 pm wrote:
> >
> > Of course, it's obvious that they have designed it for the target speeds. Neither
> > of your conclusions regarding L1 latency follow from that, however.
>
> So they designed with a 4 cycle load latency when they could have used a 3 or 2 cycle load latency?
>

Yes, of course they could implement a 2 or 3 cycle latency or an 8 or 16 cycle latency or whatever they want. Whether it makes sense is another question! Presumably the tradeoffs involved means that only a very small range of load-to-use latency makes sense for most code on modern processes and architectures, which is why you see typical latencies in the 2-5 cycle range usually.

You'll have to me more explicit with me though, because I'm not sure what you are getting at. Your original statements both seem false, but if you want to discuss something else then be clear!