juanrga (noemail.delete@this.juanrga.com) on October 29, 2016 9:47 pm wrote:
> anon (spam.delete.delete@this.this.spam.com) on October 28, 2016 4:13 am wrote:
> > juanrga (noemail.delete@this.juanrga.com) on October 28, 2016 2:02 am wrote:
>
>

My point is that Apple can target 4GHz for some future chip, miss some few IPC percents
> compared to current designs and then recover those percents via hardware improvements.

>

Your claim doesn't make a lot of sense. The point is that frequency and IPC exist two somewhat opposite points in the multi-dimensional tradeoff space used in CPU design - more "brainy" designs may give up frequency to get more IPC. There are other dimensions too - you may be able increase IPC while holding frequency constant by moving to a new process, by increasing transitor count, by increasing power us, by deploying a novel new design, etc, etc.

The main point made was that you can't simply evaluate in a quantitative way the coefficients in this tradeoff (i.e., how much IPC you gain by reducing f) by taking an existing chip and downclocking it! That will only give a small IPC boost due to decreased relative DRAM latency (and perhaps L3 or L4 latency for systems where those caches are in a separate clock domain). The main IPC benefit to reduced frequencies is missed: the ability to use the longer clock cycles to stuff in more logic per pipeline stage, to reduce the number of pipeline stages, to increase cache sizes, whatever.

Claiming that the same logic works in reverse is nonsensical - you can't just upclock a 2 Ghz design to 4 Ghz, unless the design was terrible and left a lot on the table in the first place...