8 wide vs 6 wide

By: Travis (travis.downs.delete@this.gmail.com), October 30, 2016 7:13 pm
Room: Moderated Discussions
juanrga (noemail.delete@this.juanrga.com) on October 30, 2016 2:56 pm wrote:
> Indeed and if the core stalls would it be considered 0-wide? Evidently, there is two ways to define
> the wide, either as a kind of average, which is not very useful because it depends on the elements
> of the ensemble taken to compute the average or we define wide as the maximum allowed by the architecture.
> Thus even if Broadwell cannot sustain 8 uops per cycle, we define it as 8-wide.
>
> It is also useful to mention context; we were trying to explain the reasons why Broadwell core is much bigger
> than Hurricane core. Even if Broadwell cannot sustain 8 uops, it has all the circuitry and transistors needed
> to issue "up to" 8 uops, and that adds to the size of the core compared to a 6-wide Hurricane.

No it is not "evident" that those are the only two ways to define it, and the one you chose is totally impractical and not one I've ever heard use. Intel chips are in no equipped to sustain throughput of 8 uops or instructions or whatever. Every other part of the pipeline is thinner.

Now there is no one "right" way, but if you want to come up with a single figure (rather than breaking it down into front-end width, execution width, whatever width), I suggest something like:

The typical sustained throughput of common basic instructions.

If some few types of instructions have higher throughput (fused cmp/jmp on Intel, for example), just ignore it!

If some few types of instructions have lower throughput (anything cracked into 2+ uops and not micro-fused on Intel, for example), just ignore it!

If there are some major caveats due to differing architectures or instruction complexity, mention it!

Under that definition, recent Intel chips are 4-wide, and have been 4-wide going back to Sandy Bridge (IIRC). In fact, that is the commonly used figure. There are several bottlenecks in the front-end and perhaps back-end that prevent anything more 4-wide sustained operation.

The primary major caveat is that x86 has memory source and memory destination versions of instructions, and these can be micro-fused, and only count as 1 for the 4-wide restriction. Sometimes you can organize things so that you can use these memory source instructions to get a load "for free", and in those cases you could consider Intel chips to be closer to 5 or even 6 wide (at most, you are going to execute 2 loads per cycle).

There are a ton of secondary caveats, such as differing instruction complexities, differing conditions for achieving the "practical width", etc, etc - but as a software guy this is both a commonly used definition of width when writing code, and a practical one for comparing architectures.

Saying that Intel is 8-wide just because it has 8 EUs hiding somewhere is really taking the piss...
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              Broadwell includes LLC, just for comparisionjuanrga2016/10/23 06:09 AM
                Broadwell includes LLC, just for comparisionanon2016/10/23 07:25 AM
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                                            Broadwell includes LLC, just for comparisionanon2016/11/02 11:50 AM
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                    Broadwell includes LLC, just for comparisionanon2016/10/26 03:10 AM
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