You are all just missing each others points.
juanrga you are arguing that "overclocking" an existing design won't reduce IPC much, which is true, while everyone else is arguing that you'd need to make changes to do that which would reduce IPC.

The point is that the logic delay must smaller than the cycle time. Delay is normalized delay times 3RC or delay in FO4 times 5RC, whatever floats your boat. Either way there's process independent metric and a process and voltage dependent tau.
So assuming your delay isn't much smaller than the cycle time (wouldn't make sense) to get the cycle time lower you either have to lower the normalized delay or tau. Moving to a new node is obviously an option and should give you significantly lower tau, but we can agree that this is not an option relevant in this discussion. It's also unlikely that there's enough headroom left to just crank up the voltage and halve tau. It would also increase power consumption massively.
So if Apple wanted to design, as you said, a chip with a Hurricane CPU that runs at 4GHz they would definitely have to lower normalized delay. But how? They can't eliminate logic so stage effort must stay the same. Otherwise it wouldn't really be Hurricane anymore and IPC wouldn't be the same. That only leaves parasitic and wire delay. But there's only so much you can do there and it comes at a significant power cost too.

See the problem?
Same logic per stage = similar delay, no matter what you do
lower delay with no downsides = can't be the same logic

I absolutely believe that they can design an A10X or whatever which could run at 3.xGHz but consume far more power (not just the 40-50% expected from the higher clockrate) but I still don't see 4GHz happening. Not on 16nm. 10nm it's all fair game again.