Broadwell includes LLC, just for comparision

By: Maynard Handley (name99.delete@this.name99.org), November 1, 2016 12:37 pm
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on November 1, 2016 12:56 pm wrote:
> You are all just missing each others points.
> juanrga you are arguing that "overclocking" an existing design won't reduce IPC much, which is true,
> while everyone else is arguing that you'd need to make changes to do that which would reduce IPC.
>
> The point is that the logic delay must smaller than the cycle time. Delay is normalized
> delay times 3RC or delay in FO4 times 5RC, whatever floats your boat. Either way there's
> process independent metric and a process and voltage dependent tau.
> So assuming your delay isn't much smaller than the cycle time (wouldn't make sense) to get the
> cycle time lower you either have to lower the normalized delay or tau. Moving to a new node is
> obviously an option and should give you significantly lower tau, but we can agree that this is
> not an option relevant in this discussion. It's also unlikely that there's enough headroom left
> to just crank up the voltage and halve tau. It would also increase power consumption massively.
> So if Apple wanted to design, as you said, a chip with a Hurricane CPU that runs at 4GHz they would definitely
> have to lower normalized delay. But how? They can't eliminate logic so stage effort must stay the same. Otherwise
> it wouldn't really be Hurricane anymore and IPC wouldn't be the same. That only leaves parasitic and wire
> delay. But there's only so much you can do there and it comes at a significant power cost too.
>
> See the problem?
> Same logic per stage = similar delay, no matter what you do
> lower delay with no downsides = can't be the same logic
>
> I absolutely believe that they can design an A10X or whatever which could run at 3.xGHz
> but consume far more power (not just the 40-50% expected from the higher clockrate) but
> I still don't see 4GHz happening. Not on 16nm. 10nm it's all fair game again.
>

Not necessarily.
Your argument relies on "So assuming your delay isn't much smaller than the cycle time (wouldn't make sense)". Is that ALWAYS a reasonable assumption?

I can think of two counter-points:

(a) The important point is that there is a third constraint, namely power. You may be running at a lower frequency that you could, even a substantially lower frequency, to meet a power budget. This is hardly unusual. iPhone 1 ran its 620MHz core underclocked to 412MHz, and I would not be surprised if the S1 and S2 CPUs (Apple Watch CPUs) are running at substantially below what they're capable of.

Which gets us to
(b) There isn't enough time to optimize the design. YES, we all agree that in a perfect world, what I've described in (a) does not make sense. An optimal design would, in fact, constantly rebalance pipeline stages and expand the amount of work done in some stages or the size of some structures (thereby increasing IPC), until the cycle time has expanded to the frequency at which your power budget requires you to run.
But in the real world there's never enough time; and there's especially not enough time when the entire design environment is changing madly around you. You're guessing at the power budget you'll have in three or four years, along with the process parameters, along with the likely timings of various micro-architectural innovations you've added. You do the best you can, while adding in a whole lot of margin.
IMHO there's no reason to believe that, freed of the power constraint and able to exploit that margin, the majority of the chips can't run substantially (say at least 30%) faster, and if you bin for some golden chips, some perhaps even 50% faster. Truth is, we all have no clue how much margin Apple put into their design based on these different concerns I have raised.

Part of the problem, I suspect, is a clash of cultures. The server folks here, and even the desktop folks, come from a tradition where the power constraint has been somewhat secondary; their past has been one of designing what was believed to be an optimal pipeline at the time (based on things like FO4 delays vs RC delays), and shipping the result at the fastest frequency it would run at. Mobile starts from a different place, where the power constraint is the thing that cannot be compromised, and you dial down frequency until you hit the power constraint, rather than dialing up frequency until you exceed the "time-to-settle" in your twitchiest pipeline stage.


(It should go without saying, and would in other environments..., that I'm not especially interested in making specific claims, which will likely never be tested, as to whether a particular CPU would run at a particular frequency if it were somehow hooked up. I'm interested in the general conceptual point.)

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                                  Broadwell includes LLC, just for comparisionMaynard Handley2016/11/01 12:37 PM
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                                      Broadwell includes LLC, just for comparisionMaynard Handley2016/11/01 06:30 PM
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