Broadwell includes LLC, just for comparision

By: Maynard Handley (name99.delete@this.name99.org), November 2, 2016 9:23 am
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on November 2, 2016 6:15 am wrote:
> Maynard Handley (name99.delete@this.name99.org) on November 1, 2016 7:30 pm wrote:
> > anon (spam.delete.delete@this.this.spam.com) on November 1, 2016 4:22 pm wrote:
> > > Of course it's not always a safe assumption.
> > >
> > > But in this case where the design target (device and therefore power budget)
> > > was known years in advance, it's not a completely new architecture, they've
> > > done a CPU on the same process before so none of the great unknowns apply.
> > >
> > > I'm sure they would have realised soon enough if they overshot their target massively and then went
> > > for higher frequencies and lower voltages to use that headroom and stay within the power budget.
> > >
> > > Really there's only two things we'd need to know:
> > > 1. tau vs voltage for 16FF+
> > > 2. stock voltage for the A10.
> > >
> > > Of course that still won't quite be the maximum but we'd have a minimum figure as to how far
> > > you could push it with a desktop/server power budget (essentially unlimited in this case).
> >
> > Since we don't have access to that information, we have to use alternative methods.
> >
> > We can guess at some level of the TARGET upper frequency by assuming that the A9X:A9 frequency ratio will
> > carry over to the A10X. Is this a perfect assumption? Of
> > course not, but it's the best we have. This assumes,
> > essentially, that the A10X is the design target frequency/power,
> > and the A10 is frequency downscaled version
> > (perhaps with tweaks like lower power transistors used in a few places that were considered safe.)
> >
> > If we do this, we get an assumed A10X 16FF frequency of 2.25/1.85*2.35=2.85GHz.
> > Throw in a free frequency scaling of 20% as TSMC has offered up for 10nm and we get to 3.4GHz.
> > (Obviously that frequency scaling is making assumptions about both transistor performance
> > scaling and RC scaling. You can quibble about this, but let's assume that TSMC are speaking
> > honestly, not making legally correct but technically useless claims --- they are, after all,
> > in the business of satisfying a wide customer base rather than pissing them off.)
> >
> > As I have said before, these are not outrageous assumptions, but they
> > get us to an impressive frequency. Not 4GHz, sure, but not bad.
> >
>
> I have honestly no idea where you're trying to go with this.
>
> We're not trying to prove that Apple can eventually reach 4GHz a few nodes down the road.
>
> The point was that the A10 CPU, even with all power constraints removed, will never match
> Broadwell/Skylake in clockrate. I am absolutely sure that the A10 got higher logic delay.
> So juanrga's argument that the A10 would be competitive at 4GHz is moot because it can not
> reach that without moving to a new node which would give Intel the same advantages.

The point was to try to put some real numbers to a he-said, she-said argument.
Is 4GHz a realistic possibility? Well, 3.4GHz IS a realistic possibility as the shipping frequency. The question, then, as per my earlier comment, is how much timing margin did Apple build in that over-exceeds an optimized CPU meeting the iPad power budget, because of various uncertainties. If that margin is of order 20%, then, yes, the A10X could reach 4GHz (subject to all the assumptions laid out here).
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