anon (spam.delete.delete@this.this.spam.com) on November 4, 2016 3:38 am wrote:
> juanrga (noemail.delete@this.juanrga.com) on November 3, 2016 12:35 pm wrote:
> > anon (spam.delete.delete@this.this.spam.com) on November 1, 2016 1:00 pm wrote:
> > > juanrga (noemail.delete@this.juanrga.com) on October 31, 2016 4:55 am wrote:
> > > > Travis (travis.downs.delete@this.gmail.com) on October 30, 2016 7:13 pm wrote:
> > > > > juanrga (noemail.delete@this.juanrga.com) on October 30, 2016 2:56 pm wrote:
> > > > > > Indeed and if the core stalls would it be considered 0-wide? Evidently, there is two ways to define
> > > > > > the wide, either as a kind of average, which is not very useful because it depends on the elements
> > > > > > of the ensemble taken to compute the average or we define wide as the maximum allowed by the architecture.
> > > > > > Thus even if Broadwell cannot sustain 8 uops per cycle, we define it as 8-wide.
> > > > > >
> > > > > > It is also useful to mention context; we were trying to
> > > > > > explain the reasons why Broadwell core is much bigger
> > > > > > than Hurricane core. Even if Broadwell cannot sustain 8
> > > > > > uops, it has all the circuitry and transistors needed
> > > > > > to issue "up to" 8 uops, and that adds to the size of the core compared to a 6-wide Hurricane.
> > > > >
> > > > > No it is not "evident" that those are the only two ways to define it, and the one you chose is
> > > > > totally impractical and not one I've ever heard use.
> > > >
> > > > You would open your hears then, because I am not the first
> > > > to claim that Haswell is 8-wide and Cyclone is 6-wide.
> > > >
> > > > http://www.lighterra.com/papers/modernmicroprocessors/#multipleissuesuperscalar
> > > >
> > > >
> > > >
> > > > https://hal.inria.fr/hal-01193178/document
> > > >
> > > > And so on...
> > >
> > > Don't use VISC marketing. Please. It's such a trainwreck.
> > > Remember this? http://images.anandtech.com/doci/10025/Presentation%20%2810%29.jpg
> > >
> > > I mean I respect what they are doing and I'm pretty sure they know
> > > what they're doing, but their marketing department? God no.
> >
> > (i)
> > I have given three resources. Those aren't all that exist, but are three easy to find online and link here.
> >
> > (ii)
> > I know Soft Machines marketing. I have criticized their marketing claims about VISC in
> > threads available in this site. I wasn't quoting that kind of marketing, but only the
> > slide reporting the wides of different available cores made by other companies. Their
> > claims about the wide of different cores agree with the other resources provided.
>
> Ok, let's say your 1st and 2nd source are right. Didn't find anything
> interesting in the 3rd, maybe you could point me to a page.

First page:

[...] while the more recent Intel Haswell microarchitecture can issue 8 micro-ops per cycle from a 60-entry issue buffer [Intel 2014].

> So the A7/A8 is 6 wide, Haswell/Broadwell are 8 wide.
>
> Now you need to explain why that means that the A10 is still
> 6 wide even though it got significantly higher IPC.

IPC depends on the issue width (and in other microarchitectural elements) through a series of parameters [1] that depend on both microarchitecture details and the program being executed.

Two designs can be both 6-wide and one be significantly faster than other clock-for-clock, due to having better parameters (for instance more accurate branch prediction hardware).

[1] L1 i-cache misses, branch mispredictions, nonoverlapping long d-cache L2 misses, latch overhead, pipeline depth,...