juanrga (noemail.delete@this.juanrga.com) on November 6, 2016 4:06 pm wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 6, 2016 4:15 am wrote:
> > juanrga (noemail.delete@this.juanrga.com) on November 4, 2016 4:39 pm wrote:
> > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 4, 2016 1:12 pm wrote:
> > > > anon (spam.delete.delete@this.this.spam.com) on November 4, 2016 6:12 am wrote:
> > > > > Yes, but I still don't see any reason why that means the A10 is 6 wide.
> > > > >
> > > > > If Sandy/Ivy Bridge is 6 wide then that doesn't mean Haswell/Broadwell is 6 wide.
> > > >
> > > > Neither are 6-wide using the standard definition.
> > >
> > > If you bother to read one of the resources given (the first link
> > > I gave), you will learn that there is no "standard" definition:
> >
> > Actually that same link does give a standard definition:
> >
> >

The number of instructions able to be issued, executed or completed per cycle is called a processor's
> > width. Note that the issue width is less than the number of functional units – this is typical.

>
> Now continue reading the reference until you get to the point where he discusses if Haswell
> would be considered 4-wide, 5-wide, or 8-wide, why it depends on what definition of "wide"
> you use,

No the definition by itself is clear. Instructions are instructions, there is no room for argument. No Intel core can decode/execute 8 instructions per cycle. Apple A7 can do 6, Haswell can do 4, it's as simple as that.

> and why he choses 8-wide (as myself did, as the other references given also did).

The reason some people choose 8-wide is to pretend Intel's cores are wider than other CPUs. When you look internally both Apple A7 and Cortex-A57 are wider than Haswell.

In fact Apple A7 is wider than Haswell in every regard. So anyone claiming Haswell is 8 wide but A7 is only 6 wide is simply lying because by the same measure A7 is actually 9 wide.

> > So it's the number of instructions that one can process, not micro-ops
> > (as those vary significantly with the microarchitecture).
> >
>
> The issue is that what you call "instructions" is not what is reordered, issued,
> executed, tracked, and retired in the metal of a modern chip as Haswell, or
> Cyclone, or A72, or Hurricane, or Zen, or Vulcan, or Kaby Lake, or...

There is an almost 1:1 correspondence between instructions and micro-ops, so yes instructions are what matters.

Wilco