David Kanter (dkanter.delete@this.realworldtech.com) on November 7, 2016 7:43 pm wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 7, 2016 2:45 am wrote:
> > juanrga (noemail.delete@this.juanrga.com) on November 6, 2016 4:06 pm wrote:
> > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 6, 2016 4:15 am wrote:
> > > > juanrga (noemail.delete@this.juanrga.com) on November 4, 2016 4:39 pm wrote:
> > > > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 4, 2016 1:12 pm wrote:
> > > > > > anon (spam.delete.delete@this.this.spam.com) on November 4, 2016 6:12 am wrote:
> > > > > > > Yes, but I still don't see any reason why that means the A10 is 6 wide.
> > > > > > >
> > > > > > > If Sandy/Ivy Bridge is 6 wide then that doesn't mean Haswell/Broadwell is 6 wide.
> > > > > >
> > > > > > Neither are 6-wide using the standard definition.
> > > > >
> > > > > If you bother to read one of the resources given (the first link
> > > > > I gave), you will learn that there is no "standard" definition:
> > > >
> > > > Actually that same link does give a standard definition:
> > > >
> > > >

The number of instructions able to be issued, executed or completed per cycle is called a processor's
> > > > width. Note that the issue width is less than the number of functional units – this is typical.

> > >
> > > Now continue reading the reference until you get to the point where he discusses if Haswell
> > > would be considered 4-wide, 5-wide, or 8-wide, why it depends on what definition of "wide"
> > > you use,
> >
> > No the definition by itself is clear. Instructions are instructions, there
> > is no room for argument. No Intel core can decode/execute 8 instructions
> > per cycle. Apple A7 can do 6, Haswell can do 4, it's as simple as that.
>
> I believe that Intel cores can actually do 5 instructions/clock with the macro-op fusion.

Yes if you have one branch every 5 instructions. Obviously other CPUs support fusion too.

> > > and why he choses 8-wide (as myself did, as the other references given also did).
> >
> > The reason some people choose 8-wide is to pretend Intel's cores are wider than other
> > CPUs. When you look internally both Apple A7 and Cortex-A57 are wider than Haswell.
>
> Even width itself is only relevant as an approximation for IPC. Having an 8-wide CPU with
> one load/store unit is no good for general purpose code (would work for some DSP, maybe).
>
> Also, not all instructions are equal. In particular, on vector codes, AVX could give x86
> an advantage. Similarly, on spill heavy code, ARMv7 may have an advantage using LDM/STM.

Absolutely, however the effect of ISA on IPC is fairly small given one executes mostly simple operations (for example load-op is rarely used on x86). But the discussion is about width.

> > In fact Apple A7 is wider than Haswell in every regard. So anyone claiming Haswell is 8 wide
> > but A7 is only 6 wide is simply lying because by the same measure A7 is actually 9 wide.
>
> It certainly appears that the A7 has similar IPC at low frequencies.

Indeed, and it looks like A10 has even better IPC despite almost doubling frequency.

> > > > So it's the number of instructions that one can process, not micro-ops
> > > > (as those vary significantly with the microarchitecture).
> > > >
> > >
> > > The issue is that what you call "instructions" is not what is reordered, issued,
> > > executed, tracked, and retired in the metal of a modern chip as Haswell, or
> > > Cyclone, or A72, or Hurricane, or Zen, or Vulcan, or Kaby Lake, or...
> >
> > There is an almost 1:1 correspondence between instructions
> > and micro-ops, so yes instructions are what matters.
>
> The median instruction decodes to 1 uop. But when you run into nasty ones, they
> are worth noting. I would always carefully consider both uops and instructions.

Sure, but most commonly used instructions are a single micro-op in unfused domain. Stores need 2 uops after rename since Haswell.

> In fact with Intel's uop cache, it's not even clear that you measure front-end width in
> instructions anymore...it could operate solely in the uop domain for extended periods.

That's quite possible, however the renamer still has a limit of 4 macro-ops and dispatch of unfused ops is limited to 5 in Haswell and 6 in Skylake. So without macro-op fusion there is no way you can ever execute more than 4 instructions per cycle.

Wilco