1 µop per instruction is not necessary

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), November 17, 2016 12:09 pm
Room: Moderated Discussions
Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 15, 2016 2:43 am wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on November 15, 2016 2:17 am wrote:
[snip[]
>> No that doesn't follow. As well as instructions that are split there are also ones that
>> are fused, especially for constructing constants. And I'm not sure what they do about
>> unconditional branches, why should they form micro-ops at all? It is just a ratio between
>> instructions and micro-ops that almost by chance happens to be so close to 1.
>
> No it's not by chance. An OoO core emits at least 1 micro op for all instructions,
> including NOPs and even fused instructions in some cases. Pretty much all commonly
> used instructions are a single micro op, you can check this yourself.

While I agree that it is not "almost by chance" that the count of µops and instructions are so close, an OoO core does not need to emit "at least 1 micro op for all instructions". Nops can be easily fused with an adjacent instruction. Unconditional relative branches do not have to be
scheduled and an ROB can track at a granularity coarser than single instructions.

Even conditional branches can be fused with other conditional branches: two speculation checks could be merged into a single µop (two dynamic sources, one static/decode-time source). Delaying the evaluation of a high confidence branch (especially if after one or more low confidence branches) may not be particularly expensive. (I suspect that such would not be worthwhile, but it is possible that such would be an optimization.)

A trace cache can facilitate fusion and even a predecoded cache could merge operations past control flow operations. (An implicit fix-up branch cache might allow the main instruction cache to avoid replication while avoiding some reexecution. It seems the distinction between a conventional trace cache and an extensively predecoded instruction cache may become a bit fuzzy.)

With various types of fusion (and fission), scheduler µops that execute more than once, distributed execution (e.g., handling moves and zeroing in the renamer, relative address calculation in decode), variability in ROB/commitment tracking and rollback granularity, and perhaps other factors, the count of µops may not be obviously defined.
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