juanrga (noemail.delete@this.juanrga.com) on November 20, 2016 5:56 am wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 14, 2016 3:53 pm wrote:
> > juanrga (noemail.delete@this.juanrga.com) on November 14, 2016 11:12 am wrote:
> > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 7, 2016 2:45 am wrote:
> > > > juanrga (noemail.delete@this.juanrga.com) on November 6, 2016 4:06 pm wrote:
> > > > >
> > > > > Now continue reading the reference until you get to the point where he discusses if Haswell
> > > > > would be considered 4-wide, 5-wide, or 8-wide, why it depends on what definition of "wide"
> > > > > you use,
> > > >
> > > > No the definition by itself is clear. Instructions are instructions, there
> > > > is no room for argument. No Intel core can decode/execute 8 instructions
> > > > per cycle. Apple A7 can do 6, Haswell can do 4, it's as simple as that.
> > >
> > > Same advice than before. Instead stop reading, continue reading the reference until you get to the
> > > point where he discusses if Haswell would be considered 4-wide, 5-wide, or 8-wide, why it depends
> > > on what definition of "wide" you use, and why he chose 8-wide, like I did, like many others do...
> >
> > When using his wrong definition, Apple A7 is 9 wide and Cortex-A72 8 wide.
> >
> > > > > and why he choses 8-wide (as myself did, as the other references given also did).
> > > >
> > > > The reason some people choose 8-wide is to pretend Intel's cores are wider than other
> > > > CPUs. When you look internally both Apple A7 and Cortex-A57 are wider than Haswell.
> > >
> > > I guess you must be kidding.
> >
> > Nope. This is a simple undeniable fact - you can verify by reading the links I
> > posted. That makes that guy's definition of width a bit dubious doesn't it?
> >
> > > > > The issue is that what you call "instructions" is not what is reordered, issued,
> > > > > executed, tracked, and retired in the metal of a modern chip as Haswell, or
> > > > > Cyclone, or A72, or Hurricane, or Zen, or Vulcan, or Kaby Lake, or...
> > > >
> > > > There is an almost 1:1 correspondence between instructions
> > > > and micro-ops, so yes instructions are what matters.
> > > >
> > >
> > > Not even in ARM that is true. Vulcan has a 1:(1.2) ratio between
> > > ARM instructions and muops. Denver has something like 1:(1.8).
> >
> > ARM quotes micro-op ratio of 1.08 for Cortex-A72, so yes that means ~95% of executed instructions
> > are a single micro-op. Denver isn't relevant here, and we don't have any details about Vulcan.
> >
> > Wilco
>
> The ratio of ARM instructions to uops can be 1.1, 1.2, or 1.8. It depends on the microarchitecture.
> Your claim there is almost 1:1 correspondence between instructions
> and uops is false and particularly wrong for x86.

There is a dependency on microarchitecture of course, but the ratio is typically very close to 1. And yes, that's true on x86 too - 1.03 on SPECINT and 1.07 on SPECFP.

Wilco