8 wide vs 6 wide

By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), November 22, 2016 3:25 pm
Room: Moderated Discussions
juanrga (noemail.delete@this.juanrga.com) on November 22, 2016 7:49 am wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 21, 2016 4:54 pm wrote:
> > juanrga (noemail.delete@this.juanrga.com) on November 20, 2016 5:56 am wrote:
> > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 14, 2016 3:53 pm wrote:
> > > > juanrga (noemail.delete@this.juanrga.com) on November 14, 2016 11:12 am wrote:
> > > > > Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on November 7, 2016 2:45 am wrote:
> > > > > > juanrga (noemail.delete@this.juanrga.com) on November 6, 2016 4:06 pm wrote:
> > > > > > >
> > > > > > > Now continue reading the reference until you get to the point where he discusses if Haswell
> > > > > > > would be considered 4-wide, 5-wide, or 8-wide, why it depends on what definition of "wide"
> > > > > > > you use,
> > > > > >
> > > > > > No the definition by itself is clear. Instructions are instructions, there
> > > > > > is no room for argument. No Intel core can decode/execute 8 instructions
> > > > > > per cycle. Apple A7 can do 6, Haswell can do 4, it's as simple as that.
> > > > >
> > > > > Same advice than before. Instead stop reading, continue reading the reference until you get to the
> > > > > point where he discusses if Haswell would be considered 4-wide, 5-wide, or 8-wide, why it depends
> > > > > on what definition of "wide" you use, and why he chose 8-wide, like I did, like many others do...
> > > >
> > > > When using his wrong definition, Apple A7 is 9 wide and Cortex-A72 8 wide.
> > > >
> > > > > > > and why he choses 8-wide (as myself did, as the other references given also did).
> > > > > >
> > > > > > The reason some people choose 8-wide is to pretend Intel's cores are wider than other
> > > > > > CPUs. When you look internally both Apple A7 and Cortex-A57 are wider than Haswell.
> > > > >
> > > > > I guess you must be kidding.
> > > >
> > > > Nope. This is a simple undeniable fact - you can verify by reading the links I
> > > > posted. That makes that guy's definition of width a bit dubious doesn't it?
> > > >
> > > > > > > The issue is that what you call "instructions" is not what is reordered, issued,
> > > > > > > executed, tracked, and retired in the metal of a modern chip as Haswell, or
> > > > > > > Cyclone, or A72, or Hurricane, or Zen, or Vulcan, or Kaby Lake, or...
> > > > > >
> > > > > > There is an almost 1:1 correspondence between instructions
> > > > > > and micro-ops, so yes instructions are what matters.
> > > > > >
> > > > >
> > > > > Not even in ARM that is true. Vulcan has a 1:(1.2) ratio between
> > > > > ARM instructions and muops. Denver has something like 1:(1.8).
> > > >
> > > > ARM quotes micro-op ratio of 1.08 for Cortex-A72, so yes that means ~95% of executed instructions
> > > > are a single micro-op. Denver isn't relevant here, and we don't have any details about Vulcan.
> > > >
> > > > Wilco
> > >
> > > The ratio of ARM instructions to uops can be 1.1, 1.2, or 1.8. It depends on the microarchitecture.
> > > Your claim there is almost 1:1 correspondence between instructions
> > > and uops is false and particularly wrong for x86.
> >
> > There is a dependency on microarchitecture of course, but the ratio is typically very
> > close to 1. And yes, that's true on x86 too - 1.03 on SPECINT and 1.07 on SPECFP.
> >
> > Wilco
>
> 1.1 is close to 1, but 1.8 is not. About x86, your link mentions that past studies by Bandhakar
> and Ding measured different ratios, 1.2 to 1.7 for SPEC, and recent numbers found by Blem et
> al on "A Detailed Analysis of Contemporary ARM and x86 Architectures" yields average of about
> 1.3 for SPECint, with some subtests like gcc going up to 1.7 for a Sandy Bridge i7.

The 1.8 is not valid as it is a VLIW that doesn't even have micro ops. Blem's paper only claims the average is typically below 1.3. Bhandakar's paper quotes an average of 1.35 for the Pentium Pro using x87... So for old CISCy x86/x87 instructions on the first OoO x86 microarchitecture the ratio is already close to 1!

Of course even a high ratio for a particular benchmark doesn't mean anything as a single big rep movsb will skew the ratio significantly. So the vast majority of executed instructions are still a single micro-op.

Wilco
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