David Kanter (dkanter.delete@this.realworldtech.com) on January 22, 2017 9:50 pm wrote:
> dmcq (dmcq.delete@this.fano.co.uk) on January 22, 2017 1:03 pm wrote:
> > Aaron Spink (aaronspink.delete@this.notearthlink.net) on January 22, 2017 12:03 pm wrote:
> > > RichardC (tich.delete@this.pobox.com) on January 22, 2017 7:54 am wrote:
> > > >
> > > > I'm agnostic about whether ARM has a chance in some parts of the scientific computing market,
> > > > but I do know that people in that business are very willing to expend software effort to tune their
> > > > critical code for a hardware platform with good price/performance, so weakness of the ARM software
> > > > ecosystem would be less of an obstacle there than in the normal server market. And the huge market
> > > > for phone/tablet ARM-based SoCs with low power and integrated GPU's means that a good deal of the
> > > > relevant hardware design is already off-the-shelf (the big weakness being the lack of a decent
> > > > interconnect fabric, but some of the ARM server efforts have tried to address that).
> > > >
> > >
> > > Problem with the phone/tablet SoCs is you are going to have to run at least twice. I'm not
> > > aware of a single phone soc with even minimal support for ECC memory. Beyond that, you have
> > > the myriad issues of memory capacity, interconnect, etc. Not really a viable direction.
> > > The needs for an HPC server simply add cost and power to the phone/tablet SoC market.
> >
> > I'm not sure what "Problem with the phone/tablet SoCs is you are going to have to run at least
> > twice." means. Every ARM designed core has ECC support as an option as far as I'm aware,
> > even
> > the A73 which is specifically for phones rather than mission critical or server applications.
>
> That's not correct. The A12/17/73 line do not have ECC on the L1D. It's possible to get
> around this by using very robust SRAM cells, but not everyone has those lying around.
>
> David

None of the Intel cores have EEC on L1D as far as I'm aware. At least you can get it if you want with lots of the ARM cores. I think the CPU caches only use parity except for some real time ones though.