By: Michael S (already5chosen.delete@this.yahoo.com), January 23, 2017 4:50 pm
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on January 23, 2017 3:32 pm wrote:
>
> None of the Intel cores have EEC on L1D as far as I'm aware. At least you can get it if you want with
> lots of the ARM cores. I think the CPU caches only use parity except for some real time ones though.
>
Write-through caches and I-caches use simple parity. Why should not they?
But write-back caches of general-purpose CPUs used to use ECC. Intel still uses ECC on its outer caches. If I am not mistaken, they stopped using ECC on L1D only since Nehalem when they switched to different SRAM cells (8T ?).
>
> None of the Intel cores have EEC on L1D as far as I'm aware. At least you can get it if you want with
> lots of the ARM cores. I think the CPU caches only use parity except for some real time ones though.
>
Write-through caches and I-caches use simple parity. Why should not they?
But write-back caches of general-purpose CPUs used to use ECC. Intel still uses ECC on its outer caches. If I am not mistaken, they stopped using ECC on L1D only since Nehalem when they switched to different SRAM cells (8T ?).
