Michael S (already5chosen.delete@this.yahoo.com) on January 24, 2017 5:26 am wrote:
> Wilco (Wilco.Dijkstra.delete@this.ntlworld.com) on January 24, 2017 2:13 am wrote:
> > vvid (no.delete@this.hans.com) on January 24, 2017 1:55 am wrote:
> > > Aaron Spink (aaronspink.delete@this.notearthlink.net) on January 23, 2017 7:02 pm wrote:
> > > > dmcq (dmcq.delete@this.fano.co.uk) on January 22, 2017 1:03 pm wrote:
> > > > > I'm not sure what "Problem with the phone/tablet SoCs is you are going to have to run at least
> > > > > twice." means. Every ARM designed core has ECC support as an option as far as I'm aware, even
> > > > > the A73 which is specifically for phones rather than mission critical or server applications.
> > > > >
> > > > That's great, what about the TB+ of main memory?
> > > >
> > >
> > > Isn't it strange to ask of TB+ DRAM from smartphone SoC?
> > > So far we have 8GB max here. Not that bad for a node.
> > > Anyway CoreLink CMN-600 supports 8chn DDR4. So it should handle 1TB(?)
> >
> > Nowadays even pure smartphone SoCs like Cortex-A73 support 1TB of memory.
>
> Is it documented?
> I mean, I fully believe that A73 can generate 40-bit address. But can it cache 1TB ? Are tags wide enough?
>
> > Cortex-A72 which
> > is also used in various servers supports up to 16TB.
>
> For starter, I'd like to see A72 server with 256 GB.
> I think, so far the biggest memory capacity we saw with ARM-designed
> core was 128 GB and even that more in theory than in practice.
>
> > High-end Xeons max out at 3TB.
> >
> > Wilco
>
> High-end Xeons support 46-bit physical address.
> With enough money you can buy 64TB Altix-UV for several years. That is, assuming you are not Chinese.
>

I had a look at the ARM documentation and I believe the A73 core supports 40 bit physical address and the A72 and A57 support 44 bit physical address