By: Michael S (already5chosen.delete@this.yahoo.com), January 24, 2017 9:47 am
Room: Moderated Discussions
dmcq (dmcq.delete@this.fano.co.uk) on January 24, 2017 8:15 am wrote:
> I meant instruction caches not 'CPU caches', sorry.
ECC on I$ would be a sign of suboptimal design.
Unless you target diamond-hard real-time.
But then, you probably don't want caches at all.
> I meant instruction caches not 'CPU caches', sorry.
ECC on I$ would be a sign of suboptimal design.
Unless you target diamond-hard real-time.
But then, you probably don't want caches at all.
